Input buildinfo: https://buildinfos.debian.net/buildinfo-pool/y/yosys/yosys_0.9-2_all.buildinfo Use metasnap for getting required timestamps New buildinfo file: /tmp/yosys-0.9-22b8gom2u/yosys_0.9-2_all.buildinfo Get source package info: yosys=0.9-2 Source URL: http://snapshot.notset.fr/mr/package/yosys/0.9-2/srcfiles?fileinfo=1 env -i PATH=/usr/sbin:/usr/bin:/sbin:/bin TMPDIR=/tmp mmdebstrap --arch=amd64 --include=autoconf=2.69-14 automake=1:1.16.3-2 autopoint=0.21-4 autotools-dev=20180224.1+nmu1 base-files=11.1 base-passwd=3.5.51 bash=5.1-3+b1 berkeley-abc=1.01+20191006git52a8ebb+dfsg-1 binutils=2.35.2-2 binutils-common=2.35.2-2 binutils-x86-64-linux-gnu=2.35.2-2 bison=2:3.7.6+dfsg-1 bsdextrautils=2.36.1-8 bsdutils=1:2.36.1-8 build-essential=12.9 bzip2=1.0.8-4 coreutils=8.32-4+b1 cpp=4:10.2.1-1 cpp-10=10.2.1-6 dash=0.5.11+git20210120+802ebd4-1 debconf=1.5.77 debhelper=13.3.4 debianutils=4.11.2 dh-autoreconf=20 dh-python=4.20201102+nmu1 dh-strip-nondeterminism=1.12.0-1 diffutils=1:3.7-5 dpkg=1.20.9 dpkg-dev=1.20.9 dwz=0.14-1 file=1:5.39-3 findutils=4.8.0-1 flex=2.6.4-8 fontconfig=2.13.1-4.2 fontconfig-config=2.13.1-4.2 fonts-dejavu-core=2.37-2 fonts-gfs-baskerville=1.1-6 fonts-gfs-porson=1.1-7 fonts-lmodern=2.004.5-6.1 g++=4:10.2.1-1 g++-10=10.2.1-6 gawk=1:5.1.0-1 gcc=4:10.2.1-1 gcc-10=10.2.1-6 gcc-10-base=10.2.1-6 gettext=0.21-4 gettext-base=0.21-4 graphviz=2.42.2-5 grep=3.6-1 groff-base=1.22.4-6 gzip=1.10-4 hostname=3.23 init-system-helpers=1.60 intltool-debian=0.35.0+20060710.5 iverilog=11.0-1 libacl1=2.2.53-10 libann0=1.1.2+doc-7 libapache-pom-java=18-1 libarchive-zip-perl=1.68-1 libasan6=10.2.1-6 libatomic1=10.2.1-6 libattr1=1:2.4.48-6 libaudit-common=1:3.0-2 libaudit1=1:3.0-2 libbinutils=2.35.2-2 libblkid1=2.36.1-8 libbrotli1=1.0.9-2+b2 libbsd0=0.11.3-1 libbz2-1.0=1.0.8-4 libc-bin=2.31-13 libc-dev-bin=2.31-13 libc6=2.31-13 libc6-dev=2.31-13 libcairo2=1.16.0-5 libcap-ng0=0.7.9-2.2+b1 libcc1-0=10.2.1-6 libcdt5=2.42.2-5 libcgraph6=2.42.2-5 libcom-err2=1.46.2-2 libcommons-logging-java=1.2-2 libcommons-parent-java=43-1 libcrypt-dev=1:4.4.18-5 libcrypt1=1:4.4.18-5 libctf-nobfd0=2.35.2-2 libctf0=2.35.2-2 libdatrie1=0.2.13-1 libdb5.3=5.3.28+dfsg1-0.8 libdebconfclient0=0.260 libdebhelper-perl=13.3.4 libdeflate0=1.7-1 libdpkg-perl=1.20.9 libelf1=0.183-3 libexpat1=2.2.10-2 libffi-dev=3.3-6 libffi7=3.3-6 libfile-stripnondeterminism-perl=1.12.0-1 libfontbox-java=1:1.8.16-2 libfontconfig1=2.13.1-4.2 libfontenc1=1:1.1.4-1 libfreetype6=2.10.4+dfsg-1 libfribidi0=1.0.8-2 libgcc-10-dev=10.2.1-6 libgcc-s1=10.2.1-6 libgcrypt20=1.8.7-6 libgd3=2.3.0-2 libgdbm-compat4=1.19-2 libgdbm6=1.19-2 libglib2.0-0=2.66.8-1 libgmp10=2:6.2.1+dfsg-1 libgomp1=10.2.1-6 libgpg-error0=1.38-2 libgraphite2-3=1.3.14-1 libgssapi-krb5-2=1.18.3-6 libgts-0.7-5=0.7.6+darcs121130-4+b1 libgvc6=2.42.2-5 libgvpr2=2.42.2-5 libharfbuzz0b=2.7.4-1 libice6=2:1.0.10-1 libicu67=67.1-7 libisl23=0.23-1 libitm1=10.2.1-6 libjbig0=2.1-3.1+b2 libjpeg62-turbo=1:2.0.6-4 libk5crypto3=1.18.3-6 libkeyutils1=1.6.1-2 libkpathsea6=2020.20200327.54578-7 libkrb5-3=1.18.3-6 libkrb5support0=1.18.3-6 liblab-gamut1=2.42.2-5 liblsan0=10.2.1-6 libltdl7=2.4.6-15 liblz4-1=1.9.3-2 liblzma5=5.2.5-2 libmagic-mgc=1:5.39-3 libmagic1=1:5.39-3 libmd0=1.0.3-3 libmount1=2.36.1-8 libmpc3=1.2.0-1 libmpdec3=2.5.1-2 libmpfr6=4.1.0-3 libncurses-dev=6.2+20201114-2 libncurses6=6.2+20201114-2 libncursesw6=6.2+20201114-2 libnsl-dev=1.3.0-2 libnsl2=1.3.0-2 libpam-modules=1.4.0-9 libpam-modules-bin=1.4.0-9 libpam-runtime=1.4.0-9 libpam0g=1.4.0-9 libpango-1.0-0=1.46.2-3 libpangocairo-1.0-0=1.46.2-3 libpangoft2-1.0-0=1.46.2-3 libpaper-utils=1.1.28+b1 libpaper1=1.1.28+b1 libpathplan4=2.42.2-5 libpcre2-8-0=10.36-2 libpcre3=2:8.39-13 libpdfbox-java=1:1.8.16-2 libperl5.32=5.32.1-5 libpipeline1=1.5.3-1 libpixman-1-0=0.40.0-1 libpng16-16=1.6.37-3 libptexenc1=2020.20200327.54578-7 libpython3-stdlib=3.9.2-3 libpython3.9-minimal=3.9.2-1 libpython3.9-stdlib=3.9.2-1 libquadmath0=10.2.1-6 libreadline-dev=8.1-2 libreadline8=8.1-2 libseccomp2=2.5.1-1 libselinux1=3.1-3 libsigsegv2=2.13-1 libsm6=2:1.2.3-1 libsmartcols1=2.36.1-8 libsqlite3-0=3.34.1-3 libssl1.1=1.1.1k-1 libstdc++-10-dev=10.2.1-6 libstdc++6=10.2.1-6 libsub-override-perl=0.09-2 libsynctex2=2020.20200327.54578-7 libsystemd0=247.3-6 libtcl8.6=8.6.11+dfsg-1 libteckit0=2.5.10+ds1-3 libtexlua53=2020.20200327.54578-7 libtexluajit2=2020.20200327.54578-7 libthai-data=0.1.28-4 libthai0=0.1.28-4 libtiff5=4.2.0-1 libtinfo6=6.2+20201114-2 libtirpc-common=1.3.1-1 libtirpc-dev=1.3.1-1 libtirpc3=1.3.1-1 libtool=2.4.6-15 libtsan0=10.2.1-6 libubsan1=10.2.1-6 libuchardet0=0.0.7-1 libudev1=247.3-6 libunistring2=0.9.10-4 libuuid1=2.36.1-8 libwebp6=0.6.1-2.1 libx11-6=2:1.7.2-1 libx11-data=2:1.7.2-1 libxau6=1:1.0.9-1 libxaw7=2:1.0.13-1.1 libxcb-render0=1.14-3 libxcb-shm0=1.14-3 libxcb1=1.14-3 libxdmcp6=1:1.1.2-3 libxext6=2:1.3.3-1.1 libxi6=2:1.7.10-1 libxml2=2.9.10+dfsg-6.7 libxmu6=2:1.1.2-2+b3 libxpm4=1:3.5.12-1 libxrender1=1:0.9.10-1 libxt6=1:1.2.0-1 libzstd1=1.4.8+dfsg-2.1 libzzip-0-13=0.13.72+dfsg.1-1.1 linux-libc-dev=5.10.46-4 lmodern=2.004.5-6.1 login=1:4.8.1-1 lsb-base=11.1.0 m4=1.4.18-5 make=4.3-4.1 man-db=2.9.4-2 mawk=1.3.4.20200120-2 media-types=4.0.0 ncurses-base=6.2+20201114-2 ncurses-bin=6.2+20201114-2 patch=2.7.6-7 perl=5.32.1-5 perl-base=5.32.1-5 perl-modules-5.32=5.32.1-5 pkg-config=0.29.2-1 po-debconf=1.0.21+nmu1 preview-latex-style=12.2-1 python3=3.9.2-3 python3-distutils=3.9.2-1 python3-lib2to3=3.9.2-1 python3-minimal=3.9.2-3 python3.9=3.9.2-1 python3.9-minimal=3.9.2-1 readline-common=8.1-2 sed=4.7-1 sensible-utils=0.0.14 sysvinit-utils=2.96-7 t1utils=1.41-4 tar=1.34+dfsg-1 tcl=8.6.11+1 tcl-dev=8.6.11+1 tcl8.6=8.6.11+dfsg-1 tcl8.6-dev=8.6.11+dfsg-1 tex-common=6.16 texlive-base=2020.20210202-3 texlive-bibtex-extra=2020.20210202-3 texlive-binaries=2020.20200327.54578-7 texlive-font-utils=2020.20210202-3 texlive-fonts-extra=2020.20210202-3 texlive-fonts-recommended=2020.20210202-3 texlive-lang-greek=2020.20210202-2 texlive-latex-base=2020.20210202-3 texlive-latex-extra=2020.20210202-3 texlive-latex-recommended=2020.20210202-3 texlive-pictures=2020.20210202-3 texlive-plain-generic=2020.20210202-3 texlive-publishers=2020.20210202-3 texlive-science=2020.20210202-3 txt2man=1.7.1-1 tzdata=2021a-1 ucf=3.0043 util-linux=2.36.1-8 x11-common=1:7.7+22 xdg-utils=1.1.3-4.1 xfonts-encodings=1:1.0.4-2.1 xfonts-utils=1:7.7+6 xz-utils=5.2.5-2 zlib1g=1:1.2.11.dfsg-2 zlib1g-dev=1:1.2.11.dfsg-2 --variant=apt --aptopt=Acquire::Check-Valid-Until "false" --aptopt=Acquire::http::Dl-Limit "1000"; --aptopt=Acquire::https::Dl-Limit "1000"; --aptopt=Acquire::Retries "5"; --aptopt=APT::Get::allow-downgrades "true"; --keyring=/usr/share/keyrings/ --essential-hook=chroot "$1" sh -c "apt-get --yes install fakeroot util-linux" --essential-hook=copy-in /usr/share/keyrings/debian-archive-bullseye-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-security-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-stable.gpg /usr/share/keyrings/debian-archive-buster-automatic.gpg /usr/share/keyrings/debian-archive-buster-security-automatic.gpg /usr/share/keyrings/debian-archive-buster-stable.gpg /usr/share/keyrings/debian-archive-keyring.gpg /usr/share/keyrings/debian-archive-removed-keys.gpg /usr/share/keyrings/debian-archive-stretch-automatic.gpg /usr/share/keyrings/debian-archive-stretch-security-automatic.gpg /usr/share/keyrings/debian-archive-stretch-stable.gpg /usr/share/keyrings/debian-ports-archive-keyring-removed.gpg /usr/share/keyrings/debian-ports-archive-keyring.gpg /usr/share/keyrings/debian-keyring.gpg /etc/apt/trusted.gpg.d/ --essential-hook=chroot "$1" sh -c "rm /etc/apt/sources.list && echo 'deb http://snapshot.notset.fr/archive/debian/20210818T025459Z/ bookworm main deb-src http://snapshot.notset.fr/archive/debian/20210818T025459Z/ bookworm main deb http://snapshot.notset.fr/archive/debian/20210815T144423Z/ unstable main' >> /etc/apt/sources.list && apt-get update" --customize-hook=chroot "$1" useradd --no-create-home -d /nonexistent -p "" builduser -s /bin/bash --customize-hook=chroot "$1" env sh -c "apt-get source --only-source -d yosys=0.9-2 && mkdir -p /build/yosys-RbN6Pn && dpkg-source --no-check -x /*.dsc /build/yosys-RbN6Pn/yosys-0.9 && chown -R builduser:builduser /build/yosys-RbN6Pn" --customize-hook=chroot "$1" env --unset=TMPDIR runuser builduser -c "cd /build/yosys-RbN6Pn/yosys-0.9 && env DEB_BUILD_OPTIONS="parallel=4" LC_ALL="C.UTF-8" SOURCE_DATE_EPOCH="1629017087" DEB_BUILD_OPTIONS=nocheck dpkg-buildpackage -uc -a amd64 --build=all" --customize-hook=sync-out /build/yosys-RbN6Pn /tmp/yosys-0.9-22b8gom2u bullseye /dev/null deb http://snapshot.notset.fr/archive/debian/20210815T144423Z unstable main I: automatically chosen mode: root I: chroot architecture amd64 is equal to the host's architecture I: automatically chosen format: null I: using /tmp/mmdebstrap.W3IG6eqBvU as tempdir I: running apt-get update... I: downloading packages with apt... I: extracting archives... I: installing essential packages... I: running --essential-hook in shell: sh -c 'chroot "$1" sh -c "apt-get --yes install fakeroot util-linux"' exec /tmp/mmdebstrap.W3IG6eqBvU Reading package lists... Building dependency tree... util-linux is already the newest version (2.36.1-8). The following NEW packages will be installed: fakeroot libfakeroot 0 upgraded, 2 newly installed, 0 to remove and 0 not upgraded. Need to get 134 kB of archives. After this operation, 397 kB of additional disk space will be used. Get:1 http://snapshot.notset.fr/archive/debian/20210815T144423Z unstable/main amd64 libfakeroot amd64 1.25.3-1.1 [47.0 kB] Get:2 http://snapshot.notset.fr/archive/debian/20210815T144423Z unstable/main amd64 fakeroot amd64 1.25.3-1.1 [87.0 kB] debconf: delaying package configuration, since apt-utils is not installed Fetched 134 kB in 0s (1002 kB/s) Selecting previously unselected package libfakeroot:amd64. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 4668 files and directories currently installed.) Preparing to unpack .../libfakeroot_1.25.3-1.1_amd64.deb ... Unpacking libfakeroot:amd64 (1.25.3-1.1) ... Selecting previously unselected package fakeroot. Preparing to unpack .../fakeroot_1.25.3-1.1_amd64.deb ... Unpacking fakeroot (1.25.3-1.1) ... Setting up libfakeroot:amd64 (1.25.3-1.1) ... Setting up fakeroot (1.25.3-1.1) ... update-alternatives: using /usr/bin/fakeroot-sysv to provide /usr/bin/fakeroot (fakeroot) in auto mode Processing triggers for libc-bin (2.31-13) ... I: running special hook: copy-in /usr/share/keyrings/debian-archive-bullseye-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-security-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-stable.gpg /usr/share/keyrings/debian-archive-buster-automatic.gpg /usr/share/keyrings/debian-archive-buster-security-automatic.gpg /usr/share/keyrings/debian-archive-buster-stable.gpg /usr/share/keyrings/debian-archive-keyring.gpg /usr/share/keyrings/debian-archive-removed-keys.gpg /usr/share/keyrings/debian-archive-stretch-automatic.gpg /usr/share/keyrings/debian-archive-stretch-security-automatic.gpg /usr/share/keyrings/debian-archive-stretch-stable.gpg /usr/share/keyrings/debian-ports-archive-keyring-removed.gpg /usr/share/keyrings/debian-ports-archive-keyring.gpg /usr/share/keyrings/debian-keyring.gpg /etc/apt/trusted.gpg.d/ I: running --essential-hook in shell: sh -c 'chroot "$1" sh -c "rm /etc/apt/sources.list && echo 'deb http://snapshot.notset.fr/archive/debian/20210818T025459Z/ bookworm main deb-src http://snapshot.notset.fr/archive/debian/20210818T025459Z/ bookworm main deb http://snapshot.notset.fr/archive/debian/20210815T144423Z/ unstable main' >> /etc/apt/sources.list && apt-get update"' exec /tmp/mmdebstrap.W3IG6eqBvU Get:1 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm InRelease [94.4 kB] Hit:2 http://snapshot.notset.fr/archive/debian/20210815T144423Z unstable InRelease Ign:3 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main Sources Ign:4 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main amd64 Packages Ign:3 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main Sources Ign:4 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main amd64 Packages Ign:3 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main Sources Ign:4 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main amd64 Packages Get:3 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main Sources [11.5 MB] Get:4 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main amd64 Packages [11.2 MB] Fetched 22.8 MB in 19s (1224 kB/s) Reading package lists... I: installing remaining packages inside the chroot... I: running --customize-hook in shell: sh -c 'chroot "$1" useradd --no-create-home -d /nonexistent -p "" builduser -s /bin/bash' exec /tmp/mmdebstrap.W3IG6eqBvU I: running --customize-hook in shell: sh -c 'chroot "$1" env sh -c "apt-get source --only-source -d yosys=0.9-2 && mkdir -p /build/yosys-RbN6Pn && dpkg-source --no-check -x /*.dsc /build/yosys-RbN6Pn/yosys-0.9 && chown -R builduser:builduser /build/yosys-RbN6Pn"' exec /tmp/mmdebstrap.W3IG6eqBvU Reading package lists... NOTICE: 'yosys' packaging is maintained in the 'Git' version control system at: https://salsa.debian.org/science-team/yosys.git Please use: git clone https://salsa.debian.org/science-team/yosys.git to retrieve the latest (possibly unreleased) updates to the package. Need to get 1320 kB of source archives. Get:1 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main yosys 0.9-2 (dsc) [2498 B] Get:2 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main yosys 0.9-2 (tar) [1300 kB] Get:3 http://snapshot.notset.fr/archive/debian/20210818T025459Z bookworm/main yosys 0.9-2 (diff) [17.6 kB] Fetched 1320 kB in 1s (1183 kB/s) Download complete and in download only mode W: Download is performed unsandboxed as root as file 'yosys_0.9-2.dsc' couldn't be accessed by user '_apt'. - pkgAcquire::Run (13: Permission denied) dpkg-source: info: extracting yosys in /build/yosys-RbN6Pn/yosys-0.9 dpkg-source: info: unpacking yosys_0.9.orig.tar.gz dpkg-source: info: unpacking yosys_0.9-2.debian.tar.xz dpkg-source: info: using patch list from debian/patches/series dpkg-source: info: applying 01_gitrevision.patch dpkg-source: info: applying 02_removeabc.patch dpkg-source: info: applying 05_abc_executable.patch dpkg-source: info: applying switch-to-free-font.patch dpkg-source: info: applying manual-build.patch dpkg-source: info: applying kfreebsd-support.patch dpkg-source: info: applying 0007-Disable-pretty-build.patch dpkg-source: info: applying 0009-Some-spelling-errors-fixed.patch dpkg-source: info: applying 0010-Fix-reproducibility-of-PDF-documents-in-yosys-doc.patch dpkg-source: info: applying 0010-Fix-adding-of-sys.path-in-yosys-smtbmc.patch dpkg-source: info: applying 0011-Do-not-show-g-build-flags-in-Version-string.patch dpkg-source: info: applying 0012-Skip-non-deterministic-test-causing-random-FTBFS-on-.patch dpkg-source: info: applying 0013-Let-dpkg-buildpackage-handle-stripping-of-binaries.patch dpkg-source: info: applying 0014-Set-path-to-berkeley-abc-instead-of-relative-path-to.patch dpkg-source: info: applying 0015-Fix-gcc11-FTBFS.patch I: running --customize-hook in shell: sh -c 'chroot "$1" env --unset=TMPDIR runuser builduser -c "cd /build/yosys-RbN6Pn/yosys-0.9 && env DEB_BUILD_OPTIONS="parallel=4" LC_ALL="C.UTF-8" SOURCE_DATE_EPOCH="1629017087" DEB_BUILD_OPTIONS=nocheck dpkg-buildpackage -uc -a amd64 --build=all"' exec /tmp/mmdebstrap.W3IG6eqBvU dpkg-buildpackage: info: source package yosys dpkg-buildpackage: info: source version 0.9-2 dpkg-buildpackage: info: source distribution unstable dpkg-buildpackage: info: source changed by Nilesh Patra dpkg-source --before-build . fakeroot debian/rules clean PREFIX=/usr dh clean --with=python3 debian/rules override_dh_auto_clean make[1]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' dh_auto_clean make -j10 clean make[2]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' rm -rf share rm -rf kernel/*.pyh if test -d manual; then cd manual && sh clean.sh; fi find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f rm -f kernel/version_1979e0b.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/ice40_dsp.o passes/pmgen/peepopt.o passes/proc/proc.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/iopadmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/techmap/flowmap.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/blif/blif.o backends/btor/btor.o backends/edif/edif.o backends/firrtl/firrtl.o backends/ilang/ilang_backend.o backends/intersynth/intersynth.o backends/json/json.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_determine_init.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o techlibs/gowin/synth_gowin.o techlibs/gowin/determine_init.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/ice40/ice40_unlut.o techlibs/intel/synth_intel.o techlibs/sf2/synth_sf2.o techlibs/sf2/sf2_iobs.o techlibs/xilinx/synth_xilinx.o frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.hh frontends/ilang/ilang_parser.output frontends/ilang/ilang_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/techmap/techmap.inc techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh yosys yosys-config yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/sha1/sha1.h share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/backends/ilang/ilang_backend.h share/python3/smtio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/drams.txt share/anlogic/drams_map.v share/anlogic/dram_init_16x4.vh share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/cells_bb.v share/ecp5/drams_map.v share/ecp5/dram.txt share/ecp5/brams_map.v share/ecp5/bram.txt share/ecp5/arith_map.v share/ecp5/latches_map.v share/ecp5/bram_init_1_2_4.vh share/ecp5/bram_init_9_18_36.vh share/ecp5/bram_conn_1.vh share/ecp5/bram_conn_2.vh share/ecp5/bram_conn_4.vh share/ecp5/bram_conn_9.vh share/ecp5/bram_conn_18.vh share/gowin/cells_map.v share/gowin/cells_sim.v share/gowin/arith_map.v share/gowin/brams_map.v share/gowin/bram.txt share/gowin/drams_map.v share/gowin/dram.txt share/gowin/brams_init3.vh share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams.txt share/intel/common/brams_map.v share/intel/max10/cells_sim.v share/intel/a10gx/cells_sim.v share/intel/cyclonev/cells_sim.v share/intel/cyclone10/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/a10gx/cells_map.v share/intel/cyclonev/cells_map.v share/intel/cyclone10/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/brams.txt share/xilinx/brams_map.v share/xilinx/brams_bb.v share/xilinx/drams.txt share/xilinx/drams_map.v share/xilinx/arith_map.v share/xilinx/ff_map.v share/xilinx/lut_map.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/techmap/filterlib.o techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/ice40/brams_init.mk techlibs/xilinx/brams_init.mk .cc rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff rm -f tests/tools/cmp_tbdata make[2]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' rm -f debian/man/*.1 rm -f Makefile.conf make[1]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' dh_clean debian/rules build-indep PREFIX=/usr dh build-indep --with=python3 dh_update_autotools_config -i dh_autoreconf -i debian/rules override_dh_auto_configure make[1]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' make config-gcc make[2]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' rm -rf share rm -rf kernel/*.pyh if test -d manual; then cd manual && sh clean.sh; fi find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f rm -f kernel/version_1979e0b.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/ice40_dsp.o passes/pmgen/peepopt.o passes/proc/proc.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/iopadmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/techmap/flowmap.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/blif/blif.o backends/btor/btor.o backends/edif/edif.o backends/firrtl/firrtl.o backends/ilang/ilang_backend.o backends/intersynth/intersynth.o backends/json/json.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_determine_init.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o techlibs/gowin/synth_gowin.o techlibs/gowin/determine_init.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/ice40/ice40_unlut.o techlibs/intel/synth_intel.o techlibs/sf2/synth_sf2.o techlibs/sf2/sf2_iobs.o techlibs/xilinx/synth_xilinx.o frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.hh frontends/ilang/ilang_parser.output frontends/ilang/ilang_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/techmap/techmap.inc techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh yosys yosys-config yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/sha1/sha1.h share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/backends/ilang/ilang_backend.h share/python3/smtio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/drams.txt share/anlogic/drams_map.v share/anlogic/dram_init_16x4.vh share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/cells_bb.v share/ecp5/drams_map.v share/ecp5/dram.txt share/ecp5/brams_map.v share/ecp5/bram.txt share/ecp5/arith_map.v share/ecp5/latches_map.v share/ecp5/bram_init_1_2_4.vh share/ecp5/bram_init_9_18_36.vh share/ecp5/bram_conn_1.vh share/ecp5/bram_conn_2.vh share/ecp5/bram_conn_4.vh share/ecp5/bram_conn_9.vh share/ecp5/bram_conn_18.vh share/gowin/cells_map.v share/gowin/cells_sim.v share/gowin/arith_map.v share/gowin/brams_map.v share/gowin/bram.txt share/gowin/drams_map.v share/gowin/dram.txt share/gowin/brams_init3.vh share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams.txt share/intel/common/brams_map.v share/intel/max10/cells_sim.v share/intel/a10gx/cells_sim.v share/intel/cyclonev/cells_sim.v share/intel/cyclone10/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/a10gx/cells_map.v share/intel/cyclonev/cells_map.v share/intel/cyclone10/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/brams.txt share/xilinx/brams_map.v share/xilinx/brams_bb.v share/xilinx/drams.txt share/xilinx/drams_map.v share/xilinx/arith_map.v share/xilinx/ff_map.v share/xilinx/lut_map.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/techmap/filterlib.o techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/ice40/brams_init.mk techlibs/xilinx/brams_init.mk .cc rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff rm -f tests/tools/cmp_tbdata echo 'CONFIG := gcc' > Makefile.conf make[2]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' make[1]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' debian/rules override_dh_auto_build-indep make[1]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' sed -i 's/REPLACEWITHDATE/August 15, 2021/' manual/presentation.tex PDF_DATE=D:20210815084447Z dh_auto_build --parallel -- all manual make -j10 "INSTALL=install --strip-program=true" all manual make[2]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' [Makefile.conf] CONFIG := gcc rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc mkdir -p kernel/ mkdir -p techlibs/common gcc -o kernel/driver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.9 (git sha1 1979e0b)\"; }" > kernel/version_1979e0b.cc mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new mkdir -p kernel/ mkdir -p kernel/ mkdir -p kernel/ python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new gcc -o kernel/rtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc mkdir -p kernel/ gcc -o kernel/log.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc mkdir -p kernel/ mkdir -p kernel/ gcc -o kernel/calc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc gcc -o kernel/yosys.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_DATDIR='"/usr/share/yosys"' kernel/yosys.cc gcc -o kernel/cellaigs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc mkdir -p libs/bigint/ gcc -o kernel/celledges.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc gcc -o libs/bigint/BigIntegerAlgorithms.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerAlgorithms.cc mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc mkdir -p libs/bigint/ gcc -o libs/bigint/BigInteger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigInteger.cc mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc mkdir -p libs/bigint/ gcc -o libs/bigint/BigIntegerUtils.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerUtils.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsigned.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsigned.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsignedInABase.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsignedInABase.cc mkdir -p libs/sha1/ gcc -o libs/sha1/sha1.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp mkdir -p libs/subcircuit/ gcc -o libs/subcircuit/subcircuit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezminisat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezminisat.cc mkdir -p libs/minisat/ gcc -o libs/minisat/Options.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Options.cc mkdir -p libs/minisat/ gcc -o libs/minisat/SimpSolver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/SimpSolver.cc In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of ‘void Minisat::vec::capacity(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’: libs/minisat/Vec.h:119:13: required from ‘void Minisat::vec::growTo(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’ libs/minisat/IntMap.h:48:58: required from ‘void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]’ libs/minisat/SolverTypes.h:338:49: required from ‘void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]’ libs/minisat/SimpSolver.cc:92:28: required from here libs/minisat/Vec.h:103:33: warning: ‘void* realloc(void*, size_t)’ moving an object of non-trivially copyable type ‘class Minisat::vec’; use ‘new’ and ‘delete’ instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h:39:7: note: ‘class Minisat::vec’ declared here 39 | class vec { | ^~~ mkdir -p libs/minisat/ gcc -o libs/minisat/Solver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Solver.cc mkdir -p libs/minisat/ gcc -o libs/minisat/System.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/System.cc In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of ‘void Minisat::vec::capacity(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’: libs/minisat/Vec.h:119:13: required from ‘void Minisat::vec::growTo(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’ libs/minisat/IntMap.h:48:58: required from ‘void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]’ libs/minisat/SolverTypes.h:338:49: required from ‘void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]’ libs/minisat/Solver.cc:134:35: required from here libs/minisat/Vec.h:103:33: warning: ‘void* realloc(void*, size_t)’ moving an object of non-trivially copyable type ‘class Minisat::vec’; use ‘new’ and ‘delete’ instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h:39:7: note: ‘class Minisat::vec’ declared here 39 | class vec { | ^~~ mkdir -p frontends/aiger/ gcc -o frontends/aiger/aigerparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/aiger/aigerparse.cc mkdir -p frontends/ast/ gcc -o frontends/ast/ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast.cc mkdir -p frontends/ast/ gcc -o frontends/ast/simplify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/simplify.cc mkdir -p frontends/ast/ gcc -o frontends/ast/genrtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/genrtlil.cc mkdir -p frontends/ast/ gcc -o frontends/ast/dpicall.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/dpicall.cc mkdir -p frontends/blif/ mkdir -p frontends/ilang/ gcc -o frontends/blif/blifparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/blif/blifparse.cc bison -o frontends/ilang/ilang_parser.tab.cc -d -r all -b frontends/ilang/ilang_parser frontends/ilang/ilang_parser.y mkdir -p frontends/ilang/ flex -o frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_lexer.l mkdir -p frontends/ilang/ gcc -o frontends/ilang/ilang_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ilang/ilang_frontend.cc mkdir -p frontends/json/ gcc -o frontends/json/jsonparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/json/jsonparse.cc mkdir -p frontends/liberty/ gcc -o frontends/liberty/liberty.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/liberty/liberty.cc mkdir -p frontends/verific/ gcc -o frontends/verific/verific.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verific/verific.cc mkdir -p frontends/verilog/ bison -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y mkdir -p frontends/verilog/ flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l mkdir -p frontends/verilog/ gcc -o frontends/verilog/preproc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/const2ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc mkdir -p passes/cmds/ gcc -o passes/cmds/add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/add.cc mkdir -p passes/cmds/ gcc -o passes/cmds/delete.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/delete.cc mkdir -p passes/cmds/ gcc -o passes/cmds/design.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/design.cc mkdir -p passes/cmds/ gcc -o passes/cmds/select.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/select.cc mkdir -p passes/cmds/ gcc -o passes/cmds/show.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/show.cc mkdir -p passes/cmds/ gcc -o passes/cmds/rename.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/rename.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connect.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scatter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scatter.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setundef.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setundef.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splitnets.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitnets.cc mkdir -p passes/cmds/ gcc -o passes/cmds/stat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/stat.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setattr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setattr.cc mkdir -p passes/cmds/ gcc -o passes/cmds/copy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/copy.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splice.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scc.cc mkdir -p passes/cmds/ gcc -o passes/cmds/torder.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/torder.cc mkdir -p passes/cmds/ gcc -o passes/cmds/logcmd.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logcmd.cc mkdir -p passes/cmds/ gcc -o passes/cmds/tee.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/tee.cc mkdir -p passes/cmds/ gcc -o passes/cmds/write_file.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/write_file.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connwrappers.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connwrappers.cc mkdir -p passes/cmds/ gcc -o passes/cmds/cover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/cover.cc mkdir -p passes/cmds/ gcc -o passes/cmds/trace.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/trace.cc mkdir -p passes/cmds/ gcc -o passes/cmds/plugin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/plugin.cc mkdir -p passes/cmds/ gcc -o passes/cmds/check.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/check.cc mkdir -p passes/cmds/ gcc -o passes/cmds/qwp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/qwp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/edgetypes.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/edgetypes.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chformal.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chformal.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chtype.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chtype.cc mkdir -p passes/cmds/ gcc -o passes/cmds/blackbox.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/blackbox.cc mkdir -p passes/cmds/ gcc -o passes/cmds/ltp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/ltp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/bugpoint.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/bugpoint.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_make.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_make.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_miter.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_simple.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_simple.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_status.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_status.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_add.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_remove.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_remove.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_induct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_induct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_struct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_struct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_purge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_purge.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_mark.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_mark.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_detect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_detect.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_extract.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_expand.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_expand.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_recode.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_recode.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_info.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_info.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_export.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_export.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_map.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/hierarchy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/hierarchy.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/uniquify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/uniquify.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/submod.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/submod.cc mkdir -p passes/memory/ gcc -o passes/memory/memory.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_dff.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_share.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_collect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_collect.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_unpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_unpack.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_bram.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bram.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_map.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_memx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_memx.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_nordff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_nordff.cc mkdir -p passes/opt/ gcc -o passes/opt/opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_merge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_merge.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_muxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_muxtree.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_reduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_rmdff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_rmdff.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_clean.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_expr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_expr.cc mkdir -p passes/opt/ gcc -o passes/opt/share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/share.cc mkdir -p passes/opt/ gcc -o passes/opt/wreduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/wreduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_demorgan.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_demorgan.cc mkdir -p passes/opt/ gcc -o passes/opt/rmports.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/rmports.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_lut.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut.cc mkdir -p passes/opt/ gcc -o passes/opt/pmux2shiftx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/pmux2shiftx.cc mkdir -p passes/opt/ gcc -o passes/opt/muxpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/muxpack.cc mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_dsp_pm.h -p ice40_dsp passes/pmgen/ice40_dsp.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/peepopt_pm.h -p peepopt passes/pmgen/peepopt_shiftmul.pmg passes/pmgen/peepopt_muldiv.pmg mkdir -p passes/proc/ gcc -o passes/proc/proc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_clean.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_rmdead.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rmdead.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_init.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_init.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_arst.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_arst.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_mux.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dlatch.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dlatch.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dff.cc mkdir -p passes/sat/ gcc -o passes/sat/sat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sat.cc mkdir -p passes/sat/ gcc -o passes/sat/freduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/freduce.cc mkdir -p passes/sat/ gcc -o passes/sat/eval.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/eval.cc mkdir -p passes/sat/ gcc -o passes/sat/sim.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sim.cc mkdir -p passes/sat/ gcc -o passes/sat/miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/miter.cc mkdir -p passes/sat/ gcc -o passes/sat/expose.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/expose.cc mkdir -p passes/sat/ gcc -o passes/sat/assertpmux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/assertpmux.cc mkdir -p passes/sat/ gcc -o passes/sat/clk2fflogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/clk2fflogic.cc mkdir -p passes/sat/ gcc -o passes/sat/async2sync.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/async2sync.cc mkdir -p passes/sat/ gcc -o passes/sat/supercover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/supercover.cc mkdir -p passes/sat/ gcc -o passes/sat/fmcombine.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fmcombine.cc mkdir -p passes/sat/ gcc -o passes/sat/mutate.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/mutate.cc mkdir -p passes/sat/ gcc -o passes/sat/cutpoint.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/cutpoint.cc mkdir -p passes/techmap/ echo "// autogenerated from techlibs/common/techmap.v" > passes/techmap/techmap.inc.new echo "static char stdcells_code[] = {" >> passes/techmap/techmap.inc.new od -v -td1 -An techlibs/common/techmap.v | sed -e 's/[0-9][0-9]*/&,/g' >> passes/techmap/techmap.inc.new echo "0};" >> passes/techmap/techmap.inc.new mv passes/techmap/techmap.inc.new passes/techmap/techmap.inc mkdir -p passes/techmap/ gcc -o passes/techmap/simplemap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/simplemap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dfflibmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflibmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/maccmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/maccmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/libparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/libparse.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/abc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/iopadmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/iopadmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/hilomap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/hilomap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_fa.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_fa.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_counter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_counter.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_reduce.cc mkdir -p passes/techmap/ gcc -o passes/techmap/alumacc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dff2dffe.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dff2dffe.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/pmuxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc mkdir -p passes/techmap/ gcc -o passes/techmap/muxcover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/muxcover.cc mkdir -p passes/techmap/ gcc -o passes/techmap/aigmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/aigmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/tribuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/tribuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/lut2mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/lut2mux.cc mkdir -p passes/techmap/ gcc -o passes/techmap/nlutmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/nlutmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffsr2dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffsr2dff.cc mkdir -p passes/techmap/ gcc -o passes/techmap/shregmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/shregmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/deminout.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/deminout.cc mkdir -p passes/techmap/ gcc -o passes/techmap/insbuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/insbuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmvcp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmvcp.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/zinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/zinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dff2dffs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dff2dffs.cc mkdir -p passes/techmap/ gcc -o passes/techmap/flowmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flowmap.cc mkdir -p passes/tests/ gcc -o passes/tests/test_autotb.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_autotb.cc mkdir -p passes/tests/ gcc -o passes/tests/test_cell.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_cell.cc mkdir -p passes/tests/ gcc -o passes/tests/test_abcloop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_abcloop.cc mkdir -p backends/aiger/ gcc -o backends/aiger/aiger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/aiger.cc mkdir -p backends/blif/ gcc -o backends/blif/blif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/blif/blif.cc mkdir -p backends/btor/ gcc -o backends/btor/btor.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/btor/btor.cc mkdir -p backends/edif/ gcc -o backends/edif/edif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/edif/edif.cc mkdir -p backends/firrtl/ gcc -o backends/firrtl/firrtl.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/firrtl/firrtl.cc mkdir -p backends/ilang/ mkdir -p backends/intersynth/ gcc -o backends/ilang/ilang_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/ilang/ilang_backend.cc gcc -o backends/intersynth/intersynth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/intersynth/intersynth.cc mkdir -p backends/json/ gcc -o backends/json/json.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/json/json.cc mkdir -p backends/simplec/ gcc -o backends/simplec/simplec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc mkdir -p backends/smt2/ gcc -o backends/smt2/smt2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc mkdir -p backends/smv/ gcc -o backends/smv/smv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc mkdir -p backends/spice/ gcc -o backends/spice/spice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/spice/spice.cc mkdir -p backends/table/ gcc -o backends/table/table.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/table/table.cc mkdir -p backends/verilog/ gcc -o backends/verilog/verilog_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/verilog/verilog_backend.cc mkdir -p techlibs/achronix/ gcc -o techlibs/achronix/synth_achronix.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/achronix/synth_achronix.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/synth_anlogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/synth_anlogic.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/anlogic_eqn.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_eqn.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/anlogic_determine_init.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_determine_init.cc mkdir -p techlibs/common/ gcc -o techlibs/common/synth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/synth.cc mkdir -p techlibs/common/ gcc -o techlibs/common/prep.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/prep.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/synth_coolrunner2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/synth_coolrunner2.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/coolrunner2_sop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_sop.cc mkdir -p techlibs/easic/ gcc -o techlibs/easic/synth_easic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/easic/synth_easic.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/synth_ecp5.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/synth_ecp5.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/ecp5_ffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/ecp5_ffinit.cc mkdir -p techlibs/gowin/ gcc -o techlibs/gowin/synth_gowin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/synth_gowin.cc mkdir -p techlibs/gowin/ gcc -o techlibs/gowin/determine_init.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/determine_init.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/synth_greenpak4.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/synth_greenpak4.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/greenpak4_dffinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/greenpak4_dffinv.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/synth_ice40.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/synth_ice40.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_braminit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_braminit.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_ffssr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_ffssr.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_ffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_ffinit.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_opt.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_unlut.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_unlut.cc mkdir -p techlibs/intel/ gcc -o techlibs/intel/synth_intel.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel/synth_intel.cc mkdir -p techlibs/sf2/ gcc -o techlibs/sf2/synth_sf2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/sf2/synth_sf2.cc mkdir -p techlibs/sf2/ gcc -o techlibs/sf2/sf2_iobs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/sf2/sf2_iobs.cc mkdir -p techlibs/xilinx/ gcc -o techlibs/xilinx/synth_xilinx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/synth_xilinx.cc sed -e 's#@CXXFLAGS@#-g -O2 -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \ -e 's#@CXX@#gcc#;' -e 's#@LDFLAGS@#-Wl,-z,relro -Wl,-z,now -Wl,--as-needed -L/usr/lib -rdynamic#;' -e 's#@LDLIBS@#-lstdc++ -lm -lrt -lreadline -lffi -ldl -ltcl8.6 -ltclstub8.6#;' \ -e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config chmod +x yosys-config mkdir -p passes/techmap/ gcc -o passes/techmap/filterlib.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/filterlib.cc sed 's|##yosys-sys-path##|sys.path += ["/usr/share/yosys"]|;' < backends/smt2/smtbmc.py > yosys-smtbmc.new chmod +x yosys-smtbmc.new mv yosys-smtbmc.new yosys-smtbmc mkdir -p share/include/kernel/ cp "./"/kernel/yosys.h share/include/kernel/yosys.h mkdir -p share/include/kernel/ cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h mkdir -p share/include/kernel/ cp "./"/kernel/log.h share/include/kernel/log.h mkdir -p share/include/kernel/ cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h mkdir -p share/include/kernel/ cp "./"/kernel/register.h share/include/kernel/register.h mkdir -p share/include/kernel/ cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h mkdir -p share/include/kernel/ cp "./"/kernel/celledges.h share/include/kernel/celledges.h mkdir -p share/include/kernel/ cp "./"/kernel/consteval.h share/include/kernel/consteval.h mkdir -p share/include/kernel/ mkdir -p share/include/kernel/ cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h cp "./"/kernel/modtools.h share/include/kernel/modtools.h mkdir -p share/include/kernel/ mkdir -p share/include/kernel/ cp "./"/kernel/macc.h share/include/kernel/macc.h cp "./"/kernel/utils.h share/include/kernel/utils.h mkdir -p share/include/kernel/ mkdir -p share/include/libs/ezsat/ cp "./"/kernel/satgen.h share/include/kernel/satgen.h cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h mkdir -p share/include/libs/ezsat/ mkdir -p share/include/libs/sha1/ cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h mkdir -p share/include/passes/fsm/ mkdir -p share/include/frontends/ast/ cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h mkdir -p share/include/backends/ilang/ cp "./"/backends/ilang/ilang_backend.h share/include/backends/ilang/ilang_backend.h mkdir -p share/python3 mkdir -p share/achronix/speedster22i/ cp "./"/backends/smt2/smtio.py share/python3/smtio.py cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v mkdir -p share/achronix/speedster22i/ mkdir -p share/anlogic cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/drams.txt share/anlogic/drams.txt mkdir -p share/anlogic cp "./"/techlibs/anlogic/drams_map.v share/anlogic/drams_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/dram_init_16x4.vh share/anlogic/dram_init_16x4.vh mkdir -p share cp "./"/techlibs/common/simlib.v share/simlib.v mkdir -p share mkdir -p share cp "./"/techlibs/common/simcells.v share/simcells.v cp "./"/techlibs/common/techmap.v share/techmap.v mkdir -p share cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v mkdir -p share cp "./"/techlibs/common/adff2dff.v share/adff2dff.v mkdir -p share mkdir -p share cp "./"/techlibs/common/dff2ff.v share/dff2ff.v cp "./"/techlibs/common/gate2lut.v share/gate2lut.v mkdir -p share mkdir -p share cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v cp "./"/techlibs/common/cells.lib share/cells.lib mkdir -p share/coolrunner2 mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v mkdir -p share/coolrunner2 mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v cp "./"/techlibs/ecp5/drams_map.v share/ecp5/drams_map.v mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/dram.txt share/ecp5/dram.txt mkdir -p share/ecp5 cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v cp "./"/techlibs/ecp5/bram.txt share/ecp5/bram.txt mkdir -p share/ecp5 cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v mkdir -p techlibs/ecp5 python3 techlibs/ecp5/brams_init.py mkdir -p techlibs/ecp5 mkdir -p share/gowin python3 techlibs/ecp5/brams_connect.py cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v touch techlibs/ecp5/brams_init.mk mkdir -p share/gowin cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v mkdir -p share/gowin cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v touch techlibs/ecp5/brams_connect.mk mkdir -p share/gowin mkdir -p share/gowin cp "./"/techlibs/gowin/bram.txt share/gowin/bram.txt cp "./"/techlibs/gowin/drams_map.v share/gowin/drams_map.v mkdir -p share/gowin mkdir -p share/gowin cp "./"/techlibs/gowin/dram.txt share/gowin/dram.txt cp "./"/techlibs/gowin/brams_init3.vh share/gowin/brams_init3.vh mkdir -p share/greenpak4 mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v mkdir -p share/greenpak4 mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v mkdir -p share/greenpak4 mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v mkdir -p techlibs/ice40 mkdir -p share/intel/common python3 techlibs/ice40/brams_init.py cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v mkdir -p share/intel/common mkdir -p share/intel/common cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v cp "./"/techlibs/intel/common/brams.txt share/intel/common/brams.txt mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_map.v share/intel/common/brams_map.v mkdir -p share/intel/max10 cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v touch techlibs/ice40/brams_init.mk mkdir -p share/intel/a10gx mkdir -p share/intel/cyclonev cp "./"/techlibs/intel/a10gx/cells_sim.v share/intel/a10gx/cells_sim.v cp "./"/techlibs/intel/cyclonev/cells_sim.v share/intel/cyclonev/cells_sim.v mkdir -p share/intel/cyclone10 mkdir -p share/intel/cycloneiv cp "./"/techlibs/intel/cyclone10/cells_sim.v share/intel/cyclone10/cells_sim.v cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v mkdir -p share/intel/cycloneive mkdir -p share/intel/max10 cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v mkdir -p share/intel/a10gx mkdir -p share/intel/cyclonev cp "./"/techlibs/intel/a10gx/cells_map.v share/intel/a10gx/cells_map.v cp "./"/techlibs/intel/cyclonev/cells_map.v share/intel/cyclonev/cells_map.v mkdir -p share/intel/cyclone10 mkdir -p share/intel/cycloneiv mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cyclone10/cells_map.v share/intel/cyclone10/cells_map.v cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v mkdir -p share/sf2 mkdir -p share/sf2 cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v mkdir -p share/sf2 mkdir -p share/xilinx cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v cp "./"/techlibs/xilinx/brams.txt share/xilinx/brams.txt cp "./"/techlibs/xilinx/brams_map.v share/xilinx/brams_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/brams_bb.v share/xilinx/brams_bb.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/drams.txt share/xilinx/drams.txt mkdir -p share/xilinx cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v cp "./"/techlibs/xilinx/drams_map.v share/xilinx/drams_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v mkdir -p techlibs/xilinx mkdir -p kernel/ python3 techlibs/xilinx/brams_init.py mkdir -p kernel/ gcc -o kernel/version_1979e0b.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_1979e0b.cc mkdir -p frontends/ilang/ gcc -o kernel/register.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc gcc -o frontends/ilang/ilang_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ilang/ilang_parser.tab.cc mkdir -p frontends/ilang/ gcc -o frontends/ilang/ilang_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ilang/ilang_lexer.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc touch techlibs/xilinx/brams_init.mk mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc mkdir -p passes/pmgen/ gcc -o passes/pmgen/ice40_dsp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_dsp.cc mkdir -p passes/pmgen/ gcc -o passes/pmgen/peepopt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/peepopt.cc mkdir -p passes/techmap/ gcc -o passes/techmap/techmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-RbN6Pn/yosys-0.9=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/techmap.cc mkdir -p share/ecp5 cp techlibs/ecp5/bram_init_1_2_4.vh share/ecp5/bram_init_1_2_4.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_init_9_18_36.vh share/ecp5/bram_init_9_18_36.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_1.vh share/ecp5/bram_conn_1.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_2.vh share/ecp5/bram_conn_2.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_4.vh share/ecp5/bram_conn_4.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_9.vh share/ecp5/bram_conn_9.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_18.vh share/ecp5/bram_conn_18.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init1.vh share/ice40/brams_init1.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init2.vh share/ice40/brams_init2.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init3.vh share/ice40/brams_init3.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_36.vh share/xilinx/brams_init_36.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_32.vh share/xilinx/brams_init_32.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_18.vh share/xilinx/brams_init_18.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_16.vh share/xilinx/brams_init_16.vh mkdir -p ./ gcc -o yosys-filterlib -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -L/usr/lib -rdynamic passes/techmap/filterlib.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -ltcl8.6 -ltclstub8.6 gcc -o yosys -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -L/usr/lib -rdynamic kernel/version_1979e0b.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/celledges.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/blif/blifparse.o frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o frontends/ilang/ilang_frontend.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_rmdff.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/ice40_dsp.o passes/pmgen/peepopt.o passes/proc/proc.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/iopadmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dff2dffe.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/dffsr2dff.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dff2dffs.o passes/techmap/flowmap.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/blif/blif.o backends/btor/btor.o backends/edif/edif.o backends/firrtl/firrtl.o backends/ilang/ilang_backend.o backends/intersynth/intersynth.o backends/json/json.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_determine_init.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o techlibs/gowin/synth_gowin.o techlibs/gowin/determine_init.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_ffssr.o techlibs/ice40/ice40_ffinit.o techlibs/ice40/ice40_opt.o techlibs/ice40/ice40_unlut.o techlibs/intel/synth_intel.o techlibs/sf2/synth_sf2.o techlibs/sf2/sf2_iobs.o techlibs/xilinx/synth_xilinx.o -lstdc++ -lm -lrt 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(/usr/share/texlive/texmf-dist/tex/latex/upquote/upquote.sty) (/usr/share/texlive/texmf-dist/tex/latex/hyperref/nameref.sty (/usr/share/texlive/texmf-dist/tex/latex/refcount/refcount.sty) (/usr/share/texlive/texmf-dist/tex/generic/gettitlestring/gettitlestring.sty)) (/usr/share/texlive/texmf-dist/tex/context/base/mkii/supp-pdf.mkii [Loading MPS to PDF converter (version 2006.09.02).] ) (/usr/share/texlive/texmf-dist/tex/latex/epstopdf-pkg/epstopdf-base.sty (/usr/share/texlive/texmf-dist/tex/latex/latexconfig/epstopdf-sys.cfg)) (/usr/share/texlive/texmf-dist/tex/latex/amsfonts/umsa.fd) (/usr/share/texlive/texmf-dist/tex/latex/amsfonts/umsb.fd) (/usr/share/texlive/texmf-dist/tex/latex/inconsolata/t1zi4.fd) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) Underfull \hbox (badness 2221) in paragraph at lines 157--162 []\T1/ptm/m/n/9 The 2nd line checks the de-sign hi-er-ar-chy and in-stan-ti-ate s [1{/var/lib/texmf/fonts/map/pdftex/updmap/pdftex.map}pdfTeX warning (ext4): des tination with the same identifier (name{figure.1}) has been already used, dupli cate ignored ...shipout:D \box_use:N \l_shipout_box l.211 pdfTeX warning (ext4): destination with the same identifier (name{figure. 2}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.211 pdfTeX warning (ext4): destination with the same identifier (name{figure. 3}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.211 ] (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang2.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang3.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstlang1.sty) (/usr/share/texlive/texmf-dist/tex/latex/listings/lstmisc.sty) [2pdfTeX warning (ext4): destination with the same identifier (name{figure.4}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.403 pdfTeX warning (ext4): destination with the same identifier (name{figure. 5}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.403 pdfTeX warning (ext4): destination with the same identifier (name{figure. 6}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.403 pdfTeX warning (ext4): destination with the same identifier (name{figure. 7}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.403 ] [3pdfTeX warning (ext4): destination with the same identifier (name{fig ure.8}) has been already used, duplicate ignored ...shipout:D \box_use:N \l_shipout_box l.466 \end{document} ] (./APPNOTE_010_Verilog_to_BLIF.aux) ) (see the transcript file for additional information){/usr/share/texlive/texmf-d ist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}{/usr/share/texlive/texmf-dist/font s/enc/dvips/base/8r.enc} Output written on APPNOTE_010_Verilog_to_BLIF.pdf (3 pages, 115585 bytes). Transcript written on APPNOTE_010_Verilog_to_BLIF.log. ++ md5sum + new_md5='4a60d467c86bf7bda036c4126ef7f702 -' + '[' '4a60d467c86bf7bda036c4126ef7f702 -' '!=' '4a60d467c86bf7bda036c4126ef7f702 -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_010_Verilog_to_BLIF.pdf + mv -f APPNOTE_010_Verilog_to_BLIF.pdf.without_pdf_id APPNOTE_010_Verilog_to_BLIF.pdf + touch APPNOTE_010_Verilog_to_BLIF.ok + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f APPNOTE_011_Design_Investigation.ok -a APPNOTE_011_Design_Investigation.ok -nt APPNOTE_011_Design_Investigation.tex ']' + '[' -f APPNOTE_011_Design_Investigation/make.sh ']' + cd APPNOTE_011_Design_Investigation + bash make.sh + false + for dot_file in *.dot + pdf_file=cmos_00.pdf + dot -Tpdf -o cmos_00.pdf cmos_00.dot + for dot_file in *.dot + pdf_file=cmos_01.pdf + dot -Tpdf -o cmos_01.pdf cmos_01.dot + for dot_file in *.dot + pdf_file=example_00.pdf + dot -Tpdf -o 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pdf_file=sumprod_00.pdf + dot -Tpdf -o sumprod_00.pdf sumprod_00.dot + for dot_file in *.dot + pdf_file=sumprod_01.pdf + dot -Tpdf -o sumprod_01.pdf sumprod_01.dot + for dot_file in *.dot + pdf_file=sumprod_02.pdf + dot -Tpdf -o sumprod_02.pdf sumprod_02.dot + for dot_file in *.dot + pdf_file=sumprod_03.pdf + dot -Tpdf -o sumprod_03.pdf sumprod_03.dot + for dot_file in *.dot + pdf_file=sumprod_04.pdf + dot -Tpdf -o sumprod_04.pdf sumprod_04.dot + for dot_file in *.dot + pdf_file=sumprod_05.pdf + dot -Tpdf -o sumprod_05.pdf sumprod_05.dot + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20210815084447Z)#' cmos_00.pdf cmos_01.pdf example_00.pdf example_01.pdf example_02.pdf example_03.pdf memdemo_00.pdf memdemo_01.pdf splice.pdf submod_00.pdf submod_01.pdf submod_02.pdf submod_03.pdf sumprod_00.pdf sumprod_01.pdf sumprod_02.pdf sumprod_03.pdf sumprod_04.pdf sumprod_05.pdf + cd .. ++ '[' -f APPNOTE_011_Design_Investigation.aux ']' ++ true + old_md5= + pdflatex -shell-escape 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Transcript written on APPNOTE_012_Verilog_to_BTOR.log. ++ md5sum + new_md5='fc9dceaa63440fd2a3c080744393ba5d -' + '[' 'fc9dceaa63440fd2a3c080744393ba5d -' '!=' 'fc9dceaa63440fd2a3c080744393ba5d -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_012_Verilog_to_BTOR.pdf + mv -f APPNOTE_012_Verilog_to_BTOR.pdf.without_pdf_id APPNOTE_012_Verilog_to_BTOR.pdf + touch APPNOTE_012_Verilog_to_BTOR.ok cd manual && PDF_DATE=D:20210815084447Z bash presentation.sh + false + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux '*.snm' '*.nav' '*.toc' md5sum: '*.snm': No such file or directory md5sum: '*.nav': No such file or directory md5sum: '*.toc': No such file or directory + make -C PRESENTATION_Intro make[3]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys counter.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `counter.ys' -- 1. Executing Verilog-2005 frontend: counter.v Parsing Verilog input from `counter.v' to AST representation. Generating RTLIL representation for module `\counter'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \counter 2.2. Analyzing design hierarchy.. Top module: \counter Removed 0 unused modules. 3. Generating Graphviz representation of design. Writing dot description to `counter_00.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_00.dot' > 'counter_00.pdf.new' && mv 'counter_00.pdf.new' 'counter_00.pdf' 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter. Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\counter.$proc$counter.v:6$1'. 1/1: $0\count[1:0] 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'. created $dff cell `$procdff$8' with positive edge clock. 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'. Removing empty process `counter.$proc$counter.v:6$1'. Cleaned up 2 empty switches. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 0 unused cells and 3 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.9. Finished OPT passes. (There is nothing left to do.) 6. Executing MEMORY pass. 6.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). 6.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 6.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 6.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 6.5. Executing MEMORY_COLLECT pass (generating $mem cells). 6.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). 7. Executing OPT pass (performing simple optimizations). 7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.6. Executing OPT_RMDFF pass (remove dff with constant values). 7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 7.9. Finished OPT passes. (There is nothing left to do.) 8. Executing FSM pass (extract and optimize FSM). 8.1. Executing FSM_DETECT pass (finding FSMs in design). 8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 9. Executing OPT pass (performing simple optimizations). 9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.6. Executing OPT_RMDFF pass (remove dff with constant values). 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 9.9. Finished OPT passes. (There is nothing left to do.) 10. Generating Graphviz representation of design. Writing dot description to `counter_01.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_01.dot' > 'counter_01.pdf.new' && mv 'counter_01.pdf.new' 'counter_01.pdf' 11. Executing TECHMAP pass (map to technology primitives). 11.1. Executing Verilog-2005 frontend: Parsing Verilog input from `' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 11.2. Continuing TECHMAP pass. Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $dff. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $alu. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $xor. Using template $paramod\_90_lcu\WIDTH=2 for cells of type $lcu. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $or. No more expansions possible. 12. Executing OPT pass (performing simple optimizations). 12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.6. Executing OPT_RMDFF pass (remove dff with constant values). 12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 1 unused cells and 32 unused wires. 12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.9. Rerunning OPT passes. (Maybe there is more to do..) 12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.13. Executing OPT_RMDFF pass (remove dff with constant values). 12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.16. Finished OPT passes. (There is nothing left to do.) 13. Executing SPLITNETS pass (splitting up multi-bit signals). 14. Generating Graphviz representation of design. Writing dot description to `counter_02.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_02.dot' > 'counter_02.pdf.new' && mv 'counter_02.pdf.new' 'counter_02.pdf' 15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. create mapping for $_DFF_N_ from mapping for $_DFF_P_. final dff cell mappings: DFF _DFF_N_ (.C(~C), .D( D), .Q( Q)); DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ unmapped dff cell: $_DFF_PN0_ unmapped dff cell: $_DFF_PN1_ unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ unmapped dff cell: $_DFFSR_NNN_ unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ Mapping DFF cells in module `\counter': mapped 2 $_DFF_P_ cells to \DFF cells. 16. Executing ABC pass (technology mapping using ABC). 16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. Extracted 6 gates and 12 wires to a netlist network with 4 inputs and 2 outputs. 16.1.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_Intro/mycells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Library "demo" from "/manual/PRESENTATION_Intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + retime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 16.1.2. Re-integrating ABC results. ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: internal signals: 6 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 2 Removing temp directory. Removed 0 unused cells and 10 unused wires. 17. Generating Graphviz representation of design. 17.1. Executing Verilog-2005 frontend: mycells.v Parsing Verilog input from `mycells.v' to AST representation. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Successfully finished Verilog frontend. 17.2. Continuing show pass. Writing dot description to `counter_03.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_03.dot' > 'counter_03.pdf.new' && mv 'counter_03.pdf.new' 'counter_03.pdf' End of script. Logfile hash: a86a572a1b CPU: user 0.11s system 0.01s, MEM: 16.36 MB total, 10.59 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 20% 4x read_verilog (0 sec), 16% 9x opt_clean (0 sec), ... make[3]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9/manual/PRESENTATION_Intro' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20210815084447Z)#' PRESENTATION_Intro/counter_00.pdf PRESENTATION_Intro/counter_01.pdf PRESENTATION_Intro/counter_02.pdf PRESENTATION_Intro/counter_03.pdf + make -C PRESENTATION_ExSyn make[3]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format pdf' -- -- Executing script file `proc_01.ys' -- 1. Executing Verilog-2005 frontend: proc_01.v Parsing Verilog input from `proc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$proc_01.v:2$1 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_01.v:2$1'. 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_01.v:2$1'. 1/1: $0\Q[0:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'. created $adff cell `$procdff$2' with positive edge clock and positive level reset. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_01.v:2$1'. Cleaned up 0 empty switches. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_01.dot' > 'proc_01.pdf.new' && mv 'proc_01.pdf.new' 'proc_01.pdf' End of script. Logfile hash: db08299fbb CPU: user 0.01s system 0.00s, MEM: 15.23 MB total, 9.38 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 28% 1x show (0 sec), 26% 1x clean (0 sec), ... ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format pdf' -- -- Executing script file `proc_02.ys' -- 1. Executing Verilog-2005 frontend: proc_02.v Parsing Verilog input from `proc_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$proc_02.v:3$1 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_02.v:3$1'. 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_02.v:3$1'. 1/1: $0\Q[0:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'. Warning: Async reset value `\RV' is not constant! created $dffsr cell `$procdff$2' with positive edge clock and positive level non-const reset. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_02.v:3$1'. Cleaned up 0 empty switches. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_02.dot' > 'proc_02.pdf.new' && mv 'proc_02.pdf.new' 'proc_02.pdf' Warnings: 1 unique messages, 1 total End of script. Logfile hash: 56c089ead5 CPU: user 0.01s system 0.00s, MEM: 15.21 MB total, 9.55 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 26% 1x show (0 sec), 26% 1x clean (0 sec), ... ../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format pdf' -- -- Executing script file `proc_03.ys' -- 1. Executing Verilog-2005 frontend: proc_03.v Parsing Verilog input from `proc_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_03.v:3$1'. 1/1: $0\Y[0:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'. 3.7. Executing PROC_DFF pass (convert process syncs to FFs). 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'. Removing empty process `test.$proc$proc_03.v:3$1'. Cleaned up 2 empty switches. Removed 0 unused cells and 4 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_03.dot' > 'proc_03.pdf.new' && mv 'proc_03.pdf.new' 'proc_03.pdf' End of script. Logfile hash: fd9c05a086 CPU: user 0.01s system 0.01s, MEM: 15.21 MB total, 9.23 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 26% 1x show (0 sec), 25% 1x clean (0 sec), ... ../../yosys -p 'script opt_01.ys; show -notitle -prefix opt_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script opt_01.ys; show -notitle -prefix opt_01 -format pdf' -- -- Executing script file `opt_01.ys' -- 1. Executing Verilog-2005 frontend: opt_01.v Parsing Verilog input from `opt_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $ternary$opt_01.v:2$1. Removed 1 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. New ctrl vector for $mux cell $ternary$opt_01.v:2$2: { } Optimizing cells in module \test. Performed a total of 1 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_RMDFF pass (remove dff with constant values). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_01.dot' > 'opt_01.pdf.new' && mv 'opt_01.pdf.new' 'opt_01.pdf' End of script. Logfile hash: 946b2a57b6 CPU: user 0.01s system 0.00s, MEM: 15.21 MB total, 9.72 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 26% 3x opt_expr (0 sec), 24% 3x opt_merge (0 sec), ... ../../yosys -p 'script opt_02.ys; show -notitle -prefix opt_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script opt_02.ys; show -notitle -prefix opt_02 -format pdf' -- -- Executing script file `opt_02.ys' -- 1. Executing Verilog-2005 frontend: opt_02.v Parsing Verilog input from `opt_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_02.dot' > 'opt_02.pdf.new' && mv 'opt_02.pdf.new' 'opt_02.pdf' End of script. Logfile hash: 8ae470d74b CPU: user 0.01s system 0.00s, MEM: 15.20 MB total, 9.18 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 27% 2x opt_expr (0 sec), 19% 2x opt_merge (0 sec), ... ../../yosys -p 'script opt_03.ys; show -notitle -prefix opt_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script opt_03.ys; show -notitle -prefix opt_03 -format pdf' -- -- Executing script file `opt_03.ys' -- 1. Executing Verilog-2005 frontend: opt_03.v Parsing Verilog input from `opt_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 1 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_03.dot' > 'opt_03.pdf.new' && mv 'opt_03.pdf.new' 'opt_03.pdf' End of script. Logfile hash: e467ab0617 CPU: user 0.01s system 0.00s, MEM: 15.20 MB total, 9.36 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 23% 2x opt_expr (0 sec), 21% 2x opt_merge (0 sec), ... ../../yosys -p 'script opt_04.ys; show -notitle -prefix opt_04 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script opt_04.ys; show -notitle -prefix opt_04 -format pdf' -- -- Executing script file `opt_04.ys' -- 1. Executing Verilog-2005 frontend: opt_04.v Parsing Verilog input from `opt_04.v' to AST representation. Generating RTLIL representation for module `\test'. Warning: wire '\Q1' is assigned in a block at opt_04.v:8. Warning: wire '\Q2' is assigned in a block at opt_04.v:12. Warning: wire '\Q2' is assigned in a block at opt_04.v:14. Warning: wire '\Q3' is assigned in a block at opt_04.v:17. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$opt_04.v:10$2 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). Found async reset \ARST in `\test.$proc$opt_04.v:10$2'. Found async reset \ARST in `\test.$proc$opt_04.v:6$1'. 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$opt_04.v:16$3'. 1/1: $0\Q3[7:0] Creating decoders for process `\test.$proc$opt_04.v:10$2'. 1/1: $0\Q2[7:0] Creating decoders for process `\test.$proc$opt_04.v:6$1'. 1/1: $0\Q1[7:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q3' using process `\test.$proc$opt_04.v:16$3'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\Q2' using process `\test.$proc$opt_04.v:10$2'. created $adff cell `$procdff$5' with positive edge clock and positive level reset. Creating register for signal `\test.\Q1' using process `\test.$proc$opt_04.v:6$1'. created $adff cell `$procdff$6' with positive edge clock and positive level reset. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$opt_04.v:16$3'. Removing empty process `test.$proc$opt_04.v:10$2'. Removing empty process `test.$proc$opt_04.v:6$1'. Cleaned up 0 empty switches. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_RMDFF pass (remove dff with constant values). Removing $procdff$6 ($adff) from module test. Removing $procdff$5 ($adff) from module test. Removing $procdff$4 ($dff) from module test. Replaced 3 DFF cells. 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 3 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_RMDFF pass (remove dff with constant values). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `opt_04.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_04.dot' > 'opt_04.pdf.new' && mv 'opt_04.pdf.new' 'opt_04.pdf' Warnings: 4 unique messages, 4 total End of script. Logfile hash: 35bed86fa8 CPU: user 0.02s system 0.00s, MEM: 15.22 MB total, 9.36 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 20% 3x opt_expr (0 sec), 19% 3x opt_merge (0 sec), ... ../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format pdf' -- -- Executing script file `memory_01.ys' -- 1. Executing Verilog-2005 frontend: memory_01.v Parsing Verilog input from `memory_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_01.v:5$2'. 1/4: $0\DOUT[7:0] 2/4: $0$memwr$\mem$memory_01.v:6$1_EN[7:0]$3 3/4: $0$memwr$\mem$memory_01.v:6$1_DATA[7:0]$5 4/4: $0$memwr$\mem$memory_01.v:6$1_ADDR[0:0]$4 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$9' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$10' with positive edge clock. Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$11' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_01.v:5$2'. Cleaned up 0 empty switches. Removed 0 unused cells and 4 unused wires. 4. Executing MEMORY pass. 4.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$memwr$\mem$memory_01.v:6$7' in module `\test': merged $dff to cell. Checking cell `$memrd$\mem$memory_01.v:7$6' in module `\test': merged data $dff to cell. 4.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 4 unused cells and 5 unused wires. 4.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.5. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\mem' in module `\test': $memwr$\mem$memory_01.v:6$7 ($memwr) $memrd$\mem$memory_01.v:7$6 ($memrd) 4.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). Mapping memory cell \mem in module \test: created 2 $dff cells and 0 static cells of width 8. read interface: 1 $dff and 1 $mux cells. write interface: 2 write mux blocks. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 6 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_RMDFF pass (remove dff with constant values). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_01.dot' > 'memory_01.pdf.new' && mv 'memory_01.pdf.new' 'memory_01.pdf' End of script. Logfile hash: 6e79952879 CPU: user 0.03s system 0.01s, MEM: 15.24 MB total, 9.72 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 23% 4x opt_clean (0 sec), 18% 3x opt_expr (0 sec), ... ../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format pdf' -- -- Executing script file `memory_02.ys' -- 1. Executing Verilog-2005 frontend: memory_02.v Parsing Verilog input from `memory_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_02.v:24$13'. 1/1: $0\RD2_DATA[7:0] Creating decoders for process `\test.$proc$memory_02.v:21$11'. 1/1: $0\RD1_DATA[7:0] Creating decoders for process `\test.$proc$memory_02.v:17$7'. 1/3: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 2/3: $0$memwr$\memory$memory_02.v:19$2_DATA[7:0]$9 3/3: $0$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$8 Creating decoders for process `\test.$proc$memory_02.v:13$3'. 1/3: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 2/3: $0$memwr$\memory$memory_02.v:15$1_DATA[7:0]$5 3/3: $0$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$4 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$13'. created $dff cell `$procdff$29' with positive edge clock. Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$11'. created $dff cell `$procdff$30' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$7'. created $dff cell `$procdff$31' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$7'. created $dff cell `$procdff$32' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$7'. created $dff cell `$procdff$33' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$34' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$35' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$36' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_02.v:24$13'. Removing empty process `test.$proc$memory_02.v:21$11'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$7'. Removing empty process `test.$proc$memory_02.v:17$7'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'. Removing empty process `test.$proc$memory_02.v:13$3'. Cleaned up 2 empty switches. Removed 0 unused cells and 14 unused wires. 4. Executing MEMORY pass. 4.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). Checking cell `$memwr$\memory$memory_02.v:15$15' in module `\test': merged $dff to cell. Checking cell `$memwr$\memory$memory_02.v:19$16' in module `\test': merged $dff to cell. Checking cell `$memrd$\memory$memory_02.v:22$12' in module `\test': merged data $dff to cell. Checking cell `$memrd$\memory$memory_02.v:25$14' in module `\test': merged data $dff to cell. 4.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 8 unused cells and 10 unused wires. 4.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating write ports of memory test.memory by address: New clock domain: posedge \WR1_CLK Port 0 ($memwr$\memory$memory_02.v:15$15) has addr \WR1_ADDR. Active bits: 11111111 New clock domain: posedge \WR2_CLK Port 1 ($memwr$\memory$memory_02.v:19$16) has addr \WR2_ADDR. Active bits: 11111111 Consolidating write ports of memory test.memory using sat-based resource sharing: Port 0 ($memwr$\memory$memory_02.v:15$15) on posedge \WR1_CLK: considered Port 1 ($memwr$\memory$memory_02.v:19$16) on posedge \WR2_CLK: considered No two subsequent ports in same clock domain considered -> nothing to consolidate. 4.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.5. Executing MEMORY_COLLECT pass (generating $mem cells). Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\test': $memwr$\memory$memory_02.v:15$15 ($memwr) $memwr$\memory$memory_02.v:19$16 ($memwr) $memrd$\memory$memory_02.v:22$12 ($memrd) $memrd$\memory$memory_02.v:25$14 ($memrd) 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Consolidated identical input bits for $mux cell $procmux$23: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] } Consolidated identical input bits for $mux cell $procmux$17: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$10 [0] } Optimizing cells in module \test. Performed a total of 2 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 4 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_RMDFF pass (remove dff with constant values). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_02.dot' > 'memory_02.pdf.new' && mv 'memory_02.pdf.new' 'memory_02.pdf' End of script. Logfile hash: aa9233bc91 CPU: user 0.04s system 0.00s, MEM: 15.29 MB total, 9.44 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 26% 4x opt_clean (0 sec), 12% 1x clean (0 sec), ... ../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' -- -- Executing script file `techmap_01.ys' -- 1. Executing Verilog-2005 frontend: techmap_01.v Parsing Verilog input from `techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: techmap_01_map.v Parsing Verilog input from `techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `techmap_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'techmap_01.dot' > 'techmap_01.pdf.new' && mv 'techmap_01.pdf.new' 'techmap_01.pdf' End of script. Logfile hash: 0262846cc7 CPU: user 0.01s system 0.00s, MEM: 15.38 MB total, 9.56 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 36% 1x techmap (0 sec), 26% 1x clean (0 sec), ... ../../yosys -p 'script abc_01.ys; show -notitle -prefix abc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Running command `script abc_01.ys; show -notitle -prefix abc_01 -format pdf' -- -- Executing script file `abc_01.ys' -- 1. Executing Verilog-2005 frontend: abc_01.v Parsing Verilog input from `abc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: abc_01_cells.v Parsing Verilog input from `abc_01_cells.v' to AST representation. Generating RTLIL representation for module `\BUF'. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Generating RTLIL representation for module `\DFFSR'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \test 3.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$abc_01.v:5$1'. 1/3: $0\y[0:0] 2/3: $0\q2[2:0] 3/3: $0\q1[2:0] 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\q2' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$3' with positive edge clock. Creating register for signal `\test.\y' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\q1' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$5' with positive edge clock. 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$abc_01.v:5$1'. Cleaned up 0 empty switches. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 3 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Finished OPT passes. (There is nothing left to do.) 6. Executing TECHMAP pass (map to technology primitives). 6.1. Executing Verilog-2005 frontend: Parsing Verilog input from `' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 6.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $reduce_xor. No more expansions possible. 7. Executing ABC pass (technology mapping using ABC). 7.1. Summary of detected clock domains: 9 cells in clk=\clk, en={ } 7.2. Extracting gate netlist of module `\test' to `/input.blif'.. Found matching posedge clock domain: \clk Extracted 9 gates and 12 wires to a netlist network with 3 inputs and 1 outputs. 7.2.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_ExSyn/abc_01_cells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR". ABC: Library "demo" from "/manual/PRESENTATION_ExSyn/abc_01_cells.lib" has 4 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: 7 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + dc2 ABC: + dretime ABC: + retime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 7.2.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 2 ABC RESULTS: NAND cells: 3 ABC RESULTS: NOR cells: 3 ABC RESULTS: NOT cells: 3 ABC RESULTS: _dff_ cells: 4 ABC RESULTS: internal signals: 8 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 1 Removing temp directory. Removed 0 unused cells and 9 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `abc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'abc_01.dot' > 'abc_01.pdf.new' && mv 'abc_01.pdf.new' 'abc_01.pdf' End of script. Logfile hash: 2b2a6f2d5c CPU: user 0.05s system 0.00s, MEM: 16.14 MB total, 10.54 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 52% 5x read_verilog (0 sec), 10% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9/manual/PRESENTATION_ExSyn' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20210815084447Z)#' PRESENTATION_ExSyn/abc_01.pdf PRESENTATION_ExSyn/memory_01.pdf PRESENTATION_ExSyn/memory_02.pdf PRESENTATION_ExSyn/opt_01.pdf PRESENTATION_ExSyn/opt_02.pdf PRESENTATION_ExSyn/opt_03.pdf PRESENTATION_ExSyn/opt_04.pdf PRESENTATION_ExSyn/proc_01.pdf PRESENTATION_ExSyn/proc_02.pdf PRESENTATION_ExSyn/proc_03.pdf PRESENTATION_ExSyn/techmap_01.pdf + make -C PRESENTATION_ExAdv make[3]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys select.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `select.ys' -- 1. Executing Verilog-2005 frontend: select.v Parsing Verilog input from `select.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$select.v:7$1'. 1/2: $0\c[15:0] 2/2: $0\b[15:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\b' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.\c' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$9' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$select.v:7$1'. Cleaned up 0 empty switches. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 1 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_RMDFF pass (remove dff with constant values). 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 7 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_RMDFF pass (remove dff with constant values). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `select.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'select.dot' > 'select.pdf.new' && mv 'select.pdf.new' 'select.pdf' End of script. Logfile hash: ac335b9416 CPU: user 0.03s system 0.00s, MEM: 15.28 MB total, 9.57 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 21% 3x opt_expr (0 sec), 21% 2x opt_clean (0 sec), ... ../../yosys red_or3x1_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `red_or3x1_test.ys' -- 1. Executing Verilog-2005 frontend: red_or3x1_test.v Parsing Verilog input from `red_or3x1_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: red_or3x1_map.v Parsing Verilog input from `red_or3x1_map.v' to AST representation. Generating RTLIL representation for module `\$reduce_or'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1 for cells of type $reduce_or. Using template $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1 for cells of type $reduce_or. Using template $paramod\$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1 for cells of type $reduce_or. No more expansions possible. Removed 0 unused cells and 18 unused wires. 4. Executing SPLITNETS pass (splitting up multi-bit signals). 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend: red_or3x1_cells.v Parsing Verilog input from `red_or3x1_cells.v' to AST representation. Generating RTLIL representation for module `\OR3X1'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `red_or3x1.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'red_or3x1.dot' > 'red_or3x1.pdf.new' && mv 'red_or3x1.pdf.new' 'red_or3x1.pdf' End of script. Logfile hash: f7f7720e72 CPU: user 0.01s system 0.00s, MEM: 15.37 MB total, 9.54 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 42% 1x techmap (0 sec), 23% 4x read_verilog (0 sec), ... ../../yosys sym_mul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `sym_mul_test.ys' -- 1. Executing Verilog-2005 frontend: sym_mul_test.v Parsing Verilog input from `sym_mul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8 for cells of type $mul. No more expansions possible. Removed 0 unused cells and 6 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `sym_mul.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'sym_mul.dot' > 'sym_mul.pdf.new' && mv 'sym_mul.pdf.new' 'sym_mul.pdf' End of script. Logfile hash: 976edf2e64 CPU: user 0.01s system 0.00s, MEM: 15.23 MB total, 9.60 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 27% 4x read_verilog (0 sec), 25% 1x clean (0 sec), ... ../../yosys mymul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `mymul_test.ys' -- 1. Executing Verilog-2005 frontend: mymul_test.v Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: mymul_map.v Parsing Verilog input from `mymul_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Continuing TECHMAP pass. Using template $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2 for cells of type $mul. Using template $paramod\MYMUL\WIDTH=2 for cells of type MYMUL. No more expansions possible. Removed 0 unused cells and 10 unused wires. Renaming module \test to \test_mapped. 4. Executing Verilog-2005 frontend: mymul_test.v Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 5. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped". 6. Executing FLATTEN pass (flatten design). Using template test_mapped for cells of type test_mapped. Using template test for cells of type test. No more expansions possible. 7. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 9 cells to SAT database. Import proof-constraint: \trigger = 1'0 Final proof equation: \trigger = 1'0 Solving problem with 127 variables and 335 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ 8. Executing SPLITNETS pass (splitting up multi-bit signals). 9. Generating Graphviz representation of design. Writing dot description to `mymul.dot'. Dumping module test_mapped to page 1. Exec: dot -Tpdf 'mymul.dot' > 'mymul.pdf.new' && mv 'mymul.pdf.new' 'mymul.pdf' End of script. Logfile hash: 88e74f01d1 CPU: user 0.03s system 0.00s, MEM: 15.36 MB total, 9.94 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 32% 2x clean (0 sec), 20% 1x techmap (0 sec), ... ../../yosys mulshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `mulshift_test.ys' -- 1. Executing Verilog-2005 frontend: mulshift_test.v Parsing Verilog input from `mulshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: mulshift_map.v Parsing Verilog input from `mulshift_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Continuing TECHMAP pass. Using template $paramod\$mul\A_SIGNED=0\B_SIGNED=0\A_WIDTH=8\B_WIDTH=8\Y_WIDTH=8 for cells of type $mul. Using template $paramod$bbc3b0b87462ac640198340d7dc539ed37c95c0b\MYMUL for cells of type MYMUL. No more expansions possible. Removed 0 unused cells and 16 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `mulshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'mulshift.dot' > 'mulshift.pdf.new' && mv 'mulshift.pdf.new' 'mulshift.pdf' End of script. Logfile hash: 612c492bc0 CPU: user 0.03s system 0.01s, MEM: 15.48 MB total, 9.62 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 42% 3x clean (0 sec), 28% 1x techmap (0 sec), ... ../../yosys addshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `addshift_test.ys' -- 1. Executing Verilog-2005 frontend: addshift_test.v Parsing Verilog input from `addshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: addshift_map.v Parsing Verilog input from `addshift_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$f9d15d41450676d24e4cd1a1cce4370f40b165ac\$add for cells of type $add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `addshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'addshift.dot' > 'addshift.pdf.new' && mv 'addshift.pdf.new' 'addshift.pdf' End of script. Logfile hash: a0fd954202 CPU: user 0.01s system 0.00s, MEM: 15.24 MB total, 9.32 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 30% 1x techmap (0 sec), 25% 1x clean (0 sec), ... ../../yosys macc_simple_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `macc_simple_test.ys' -- 1. Executing Verilog-2005 frontend: macc_simple_test.v Parsing Verilog input from `macc_simple_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 3. Generating Graphviz representation of design. 3.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 3.2. Continuing show pass. Writing dot description to `macc_simple_test_00a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00a.dot' > 'macc_simple_test_00a.pdf.new' && mv 'macc_simple_test_00a.pdf.new' 'macc_simple_test_00a.pdf' 4. Executing EXTRACT pass (map subcircuits to cells). 4.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.2.3. Executing PROC_INIT pass (extract init attributes). 4.2.4. Executing PROC_ARST pass (detect async resets in processes). 4.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 4.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.2.7. Executing PROC_DFF pass (convert process syncs to FFs). 4.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 4.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 4.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 4.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$7 -> $add$macc_simple_test.v:5$2 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_simple_xmap.v:5$6 -> $mul$macc_simple_test.v:5$1 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$8 Removed 0 unused cells and 1 unused wires. 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `macc_simple_test_00b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00b.dot' > 'macc_simple_test_00b.pdf.new' && mv 'macc_simple_test_00b.pdf.new' 'macc_simple_test_00b.pdf' 6. Executing Verilog-2005 frontend: macc_simple_test_01.v Parsing Verilog input from `macc_simple_test_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 7. Executing HIERARCHY pass (managing design hierarchy). 7.1. Analyzing design hierarchy.. Top module: \test 7.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 8. Generating Graphviz representation of design. 8.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 8.2. Continuing show pass. Writing dot description to `macc_simple_test_01a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01a.dot' > 'macc_simple_test_01a.pdf.new' && mv 'macc_simple_test_01a.pdf.new' 'macc_simple_test_01a.pdf' 9. Executing EXTRACT pass (map subcircuits to cells). 9.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 9.2. Executing PROC pass (convert processes to netlists). 9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 9.2.3. Executing PROC_INIT pass (extract init attributes). 9.2.4. Executing PROC_ARST pass (detect async resets in processes). 9.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 9.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 9.2.7. Executing PROC_DFF pass (convert process syncs to FFs). 9.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 9.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 9.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 9.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$18 -> $add$macc_simple_test_01.v:5$13 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$17 -> $mul$macc_simple_test_01.v:5$11 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$19 Removed 0 unused cells and 1 unused wires. 10. Generating Graphviz representation of design. 10.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 10.2. Continuing show pass. Writing dot description to `macc_simple_test_01b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01b.dot' > 'macc_simple_test_01b.pdf.new' && mv 'macc_simple_test_01b.pdf.new' 'macc_simple_test_01b.pdf' 11. Executing Verilog-2005 frontend: macc_simple_test_02.v Parsing Verilog input from `macc_simple_test_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 12. Executing HIERARCHY pass (managing design hierarchy). 12.1. Analyzing design hierarchy.. Top module: \test 12.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 13. Generating Graphviz representation of design. 13.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 13.2. Continuing show pass. Writing dot description to `macc_simple_test_02a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02a.dot' > 'macc_simple_test_02a.pdf.new' && mv 'macc_simple_test_02a.pdf.new' 'macc_simple_test_02a.pdf' 14. Executing EXTRACT pass (map subcircuits to cells). 14.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 14.2. Executing PROC pass (convert processes to netlists). 14.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 14.2.3. Executing PROC_INIT pass (extract init attributes). 14.2.4. Executing PROC_ARST pass (detect async resets in processes). 14.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 14.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 14.2.7. Executing PROC_DFF pass (convert process syncs to FFs). 14.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 14.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 14.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 2 matches. 14.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$24 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$23 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$30 Match #1: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$25 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$22 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$31 Removed 0 unused cells and 2 unused wires. 15. Generating Graphviz representation of design. 15.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 15.2. Continuing show pass. Writing dot description to `macc_simple_test_02b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02b.dot' > 'macc_simple_test_02b.pdf.new' && mv 'macc_simple_test_02b.pdf.new' 'macc_simple_test_02b.pdf' 16. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 17. Executing HIERARCHY pass (managing design hierarchy). 17.1. Analyzing design hierarchy.. Top module: \macc_16_16_32 17.2. Analyzing design hierarchy.. Top module: \macc_16_16_32 Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_simple_xmap.dot'. Dumping module macc_16_16_32 to page 1. Exec: dot -Tpdf 'macc_simple_xmap.dot' > 'macc_simple_xmap.pdf.new' && mv 'macc_simple_xmap.pdf.new' 'macc_simple_xmap.pdf' End of script. Logfile hash: a22913d34f CPU: user 0.06s system 0.01s, MEM: 15.30 MB total, 9.85 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 30% 7x clean (0 sec), 19% 3x extract (0 sec), ... ../../yosys macc_xilinx_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `macc_xilinx_test.ys' -- 1. Executing Verilog-2005 frontend: macc_xilinx_test.v Parsing Verilog input from `macc_xilinx_test.v' to AST representation. Generating RTLIL representation for module `\test1'. Generating RTLIL representation for module `\test2'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `$__mul_wrapper'. Generating RTLIL representation for module `$__add_wrapper'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 4. Executing HIERARCHY pass (managing design hierarchy). Removed 0 unused cells and 2 unused wires. 5. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1a.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1a.dot' > 'macc_xilinx_test1a.pdf.new' && mv 'macc_xilinx_test1a.pdf.new' 'macc_xilinx_test1a.pdf' 6. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2a.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2a.dot' > 'macc_xilinx_test2a.pdf.new' && mv 'macc_xilinx_test2a.pdf.new' 'macc_xilinx_test2a.pdf' 7. Executing TECHMAP pass (map to technology primitives). 7.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 7.2. Continuing TECHMAP pass. Using template $paramod\mul_swap_ports\A_SIGNED=0\B_SIGNED=0\A_WIDTH=20\B_WIDTH=16\Y_WIDTH=42 for cells of type $mul. No more expansions possible. Removed 0 unused cells and 8 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1b.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1b.dot' > 'macc_xilinx_test1b.pdf.new' && mv 'macc_xilinx_test1b.pdf.new' 'macc_xilinx_test1b.pdf' 9. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2b.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2b.dot' > 'macc_xilinx_test2b.pdf.new' && mv 'macc_xilinx_test2b.pdf.new' 'macc_xilinx_test2b.pdf' 10. Executing TECHMAP pass (map to technology primitives). 10.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 10.2. Continuing TECHMAP pass. Using template $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=20\Y_WIDTH=42 for cells of type $mul. Using template $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42 for cells of type $add. Using template $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42 for cells of type $mul. No more expansions possible. 11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells). Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap19$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap21$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap17$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap25$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap24$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap23$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } Removed 0 unused cells and 56 unused wires. 12. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1c.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1c.dot' > 'macc_xilinx_test1c.pdf.new' && mv 'macc_xilinx_test1c.pdf.new' 'macc_xilinx_test1c.pdf' 13. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2c.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2c.dot' > 'macc_xilinx_test2c.pdf.new' && mv 'macc_xilinx_test2c.pdf.new' 'macc_xilinx_test2c.pdf' 14. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 15. Executing TECHMAP pass (map to technology primitives). 15.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 15.2. Continuing TECHMAP pass. No more expansions possible. 16. Executing TECHMAP pass (map to technology primitives). 16.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 16.2. Continuing TECHMAP pass. Using template $paramod\mul_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=18\B_WIDTH=25\Y_WIDTH=48 for cells of type $mul. Using template $paramod\add_wrap\A_SIGNED=0\B_SIGNED=0\A_WIDTH=48\B_WIDTH=48\Y_WIDTH=48 for cells of type $add. No more expansions possible. Removed 0 unused cells and 17 unused wires. 17. Executing EXTRACT pass (map subcircuits to cells). 17.1. Creating graphs for SubCircuit library. Creating needle graph needle_DSP48_MACC. Creating haystack graph haystack_$__add_wrapper. Creating haystack graph haystack_$__mul_wrapper. Creating haystack graph haystack_DSP48_MACC. Creating haystack graph haystack_test1. Creating haystack graph haystack_test2. 17.2. Running solver from SubCircuit library. Solving for needle_DSP48_MACC in haystack_$__add_wrapper. Solving for needle_DSP48_MACC in haystack_$__mul_wrapper. Solving for needle_DSP48_MACC in haystack_DSP48_MACC. Solving for needle_DSP48_MACC in haystack_test1. Solving for needle_DSP48_MACC in haystack_test2. Found 3 matches. 17.3. Substitute SubCircuits with cells. Match #0: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$35 Match #1: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$36 Match #2: (needle_DSP48_MACC in haystack_test2) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$37 Removed 0 unused cells and 6 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1d.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1d.dot' > 'macc_xilinx_test1d.pdf.new' && mv 'macc_xilinx_test1d.pdf.new' 'macc_xilinx_test1d.pdf' 19. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2d.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2d.dot' > 'macc_xilinx_test2d.pdf.new' && mv 'macc_xilinx_test2d.pdf.new' 'macc_xilinx_test2d.pdf' 20. Executing TECHMAP pass (map to technology primitives). 20.1. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `\$__mul_wrapper'. Generating RTLIL representation for module `\$__add_wrapper'. Successfully finished Verilog frontend. 20.2. Continuing TECHMAP pass. Using template $paramod\$__mul_wrapper\A_SIGNED=0\B_SIGNED=0\A_WIDTH=16\B_WIDTH=16\Y_WIDTH=42 for cells of type $__mul_wrapper. Using template $paramod\$__add_wrapper\A_SIGNED=0\B_SIGNED=0\A_WIDTH=42\B_WIDTH=42\Y_WIDTH=42 for cells of type $__add_wrapper. No more expansions possible. Removed 0 unused cells and 14 unused wires. 21. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1e.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1e.dot' > 'macc_xilinx_test1e.pdf.new' && mv 'macc_xilinx_test1e.pdf.new' 'macc_xilinx_test1e.pdf' 22. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2e.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2e.dot' > 'macc_xilinx_test2e.pdf.new' && mv 'macc_xilinx_test2e.pdf.new' 'macc_xilinx_test2e.pdf' 23. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_xmap.dot'. Dumping module DSP48_MACC to page 1. Exec: dot -Tpdf 'macc_xilinx_xmap.dot' > 'macc_xilinx_xmap.pdf.new' && mv 'macc_xilinx_xmap.pdf.new' 'macc_xilinx_xmap.pdf' End of script. Logfile hash: f74c6fae71 CPU: user 0.19s system 0.02s, MEM: 16.02 MB total, 10.27 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 47% 12x clean (0 sec), 19% 5x techmap (0 sec), ... make[3]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9/manual/PRESENTATION_ExAdv' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20210815084447Z)#' PRESENTATION_ExAdv/addshift.pdf PRESENTATION_ExAdv/macc_simple_test_00a.pdf PRESENTATION_ExAdv/macc_simple_test_00b.pdf PRESENTATION_ExAdv/macc_simple_test_01a.pdf PRESENTATION_ExAdv/macc_simple_test_01b.pdf PRESENTATION_ExAdv/macc_simple_test_02a.pdf PRESENTATION_ExAdv/macc_simple_test_02b.pdf PRESENTATION_ExAdv/macc_simple_xmap.pdf PRESENTATION_ExAdv/macc_xilinx_test1a.pdf PRESENTATION_ExAdv/macc_xilinx_test1b.pdf PRESENTATION_ExAdv/macc_xilinx_test1c.pdf PRESENTATION_ExAdv/macc_xilinx_test1d.pdf PRESENTATION_ExAdv/macc_xilinx_test1e.pdf PRESENTATION_ExAdv/macc_xilinx_test2a.pdf PRESENTATION_ExAdv/macc_xilinx_test2b.pdf PRESENTATION_ExAdv/macc_xilinx_test2c.pdf PRESENTATION_ExAdv/macc_xilinx_test2d.pdf PRESENTATION_ExAdv/macc_xilinx_test2e.pdf PRESENTATION_ExAdv/macc_xilinx_xmap.pdf PRESENTATION_ExAdv/mulshift.pdf PRESENTATION_ExAdv/mymul.pdf PRESENTATION_ExAdv/red_or3x1.pdf PRESENTATION_ExAdv/select.pdf PRESENTATION_ExAdv/sym_mul.pdf + make -C PRESENTATION_ExOth make[3]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys scrambler.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `scrambler.ys' -- 1. Executing Verilog-2005 frontend: scrambler.v Parsing Verilog input from `scrambler.v' to AST representation. Generating RTLIL representation for module `\scrambler'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler. Removed a total of 0 dead cases. 3.3. Executing PROC_INIT pass (extract init attributes). 3.4. Executing PROC_ARST pass (detect async resets in processes). 3.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'. 1/3: $1\xs[31:0] 2/3: $0\out_bit[0:0] 3/3: $0\xs[31:0] 3.6. Executing PROC_DLATCH pass (convert process syncs to latches). 3.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$12' with positive edge clock. Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$13' with positive edge clock. 3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'. Removing empty process `scrambler.$proc$scrambler.v:6$1'. Cleaned up 1 empty switch. Removed 0 unused cells and 4 unused wires. 4. Executing SUBMOD pass (moving cells to submodules as requested). 4.1. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \scrambler.. 4.2. Continuing SUBMOD pass. Creating submodule xorshift32 (\xorshift32) of module \scrambler. signal $shl$scrambler.v:11$6_Y: internal signal $shl$scrambler.v:9$2_Y: internal signal $0\xs[31:0]: output \n1 signal $1\xs[31:0]: input \n2 signal $xor$scrambler.v:9$3_Y: internal signal $shr$scrambler.v:10$4_Y: internal signal $xor$scrambler.v:10$5_Y: internal cell $xor$scrambler.v:9$3 ($xor) cell $shl$scrambler.v:9$2 ($shl) cell $shr$scrambler.v:10$4 ($shr) cell $xor$scrambler.v:10$5 ($xor) cell $shl$scrambler.v:11$6 ($shl) cell $xor$scrambler.v:11$7 ($xor) 5. Generating Graphviz representation of design. Writing dot description to `scrambler_p01.dot'. Dumping module scrambler to page 1. Exec: dot -Tpdf 'scrambler_p01.dot' > 'scrambler_p01.pdf.new' && mv 'scrambler_p01.pdf.new' 'scrambler_p01.pdf' 6. Generating Graphviz representation of design. Writing dot description to `scrambler_p02.dot'. Dumping module xorshift32 to page 1. Exec: dot -Tpdf 'scrambler_p02.dot' > 'scrambler_p02.pdf.new' && mv 'scrambler_p02.pdf.new' 'scrambler_p02.pdf' echo on yosys> cd xorshift32 yosys [xorshift32]> rename n2 in Renaming wire n2 to in in module xorshift32. yosys [xorshift32]> rename n1 out Renaming wire n1 to out in module xorshift32. yosys [xorshift32]> eval -set in 1 -show out 7. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 270369. yosys [xorshift32]> eval -set in 270369 -show out 8. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 67634689. yosys [xorshift32]> sat -set out 632435482 9. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Import set-constraint: \out = 632435482 Final constraint equation: \out = 632435482 Imported 6 cells to SAT database. Solving problem with 1119 variables and 2905 clauses.. SAT solving finished - model found: Signal Name Dec Hex Bin --------------- ----------- --------- ----------------------------------- \in 745495504 2c6f5bd0 00101100011011110101101111010000 \out 632435482 25b2331a 00100101101100100011001100011010 End of script. Logfile hash: 6c404457a8 CPU: user 0.05s system 0.00s, MEM: 16.07 MB total, 10.51 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 43% 1x sat (0 sec), 13% 1x submod (0 sec), ... ../../yosys -l equiv.log_new equiv.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `equiv.ys' -- 1. Executing Verilog-2005 frontend: ../PRESENTATION_ExSyn/techmap_01.v Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Renaming module \test to \test_mapped. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: ../PRESENTATION_ExSyn/techmap_01_map.v Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod\$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $add. No more expansions possible. 4. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test_orig" and gate cell "test_mapped". 5. Executing FLATTEN pass (flatten design). Using template test_orig for cells of type test_orig. Using template test_mapped for cells of type test_mapped. No more expansions possible. 6. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 7 cells to SAT database. Import proof for assert: $auto$miter.cc:211:create_miter_equiv$6 when 1'1. Import show expression: \in_b Import show expression: \in_a Import show expression: \trigger Import show expression: \gate_y Import show expression: \gold_y Solving problem with 945 variables and 2505 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ End of script. Logfile hash: a981646901 CPU: user 0.04s system 0.00s, MEM: 16.23 MB total, 10.51 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 77% 1x sat (0 sec), 12% 1x techmap (0 sec), ... mv equiv.log_new equiv.log ../../yosys -l axis_test.log_new axis_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) -- Executing script file `axis_test.ys' -- 1. Executing Verilog-2005 frontend: axis_master.v Parsing SystemVerilog input from `axis_master.v' to AST representation. Generating RTLIL representation for module `\axis_master'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: axis_test.v Parsing SystemVerilog input from `axis_test.v' to AST representation. Generating RTLIL representation for module `\axis_test'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master 3.2. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master Removed 0 unused modules. Module axis_test directly or indirectly contains formal properties -> setting "keep" attribute. Mapping positional arguments of cell axis_test.uut (axis_master). 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 2 switch rules as full_case in process $proc$axis_master.v:7$1 in module axis_master. Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). Found init rule in `\axis_test.$proc$axis_test.v:22$98'. Set init value: $formal$axis_test.v:22$23_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:21$96'. Set init value: $formal$axis_test.v:21$22_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:20$94'. Set init value: $formal$axis_test.v:20$21_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:19$92'. Set init value: $formal$axis_test.v:19$20_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:18$90'. Set init value: $formal$axis_test.v:18$19_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:17$88'. Set init value: $formal$axis_test.v:17$18_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:16$86'. Set init value: $formal$axis_test.v:16$17_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:15$84'. Set init value: $formal$axis_test.v:15$16_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:14$82'. Set init value: $formal$axis_test.v:14$15_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:13$80'. Set init value: $formal$axis_test.v:13$14_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:7$79'. Set init value: \aresetn = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:6$78'. Set init value: \counter = 0 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\axis_test.$proc$axis_test.v:22$98'. 1/1: $0$formal$axis_test.v:22$23_EN[0:0]$99 Creating decoders for process `\axis_test.$proc$axis_test.v:21$96'. 1/1: $0$formal$axis_test.v:21$22_EN[0:0]$97 Creating decoders for process `\axis_test.$proc$axis_test.v:20$94'. 1/1: $0$formal$axis_test.v:20$21_EN[0:0]$95 Creating decoders for process `\axis_test.$proc$axis_test.v:19$92'. 1/1: $0$formal$axis_test.v:19$20_EN[0:0]$93 Creating decoders for process `\axis_test.$proc$axis_test.v:18$90'. 1/1: $0$formal$axis_test.v:18$19_EN[0:0]$91 Creating decoders for process `\axis_test.$proc$axis_test.v:17$88'. 1/1: $0$formal$axis_test.v:17$18_EN[0:0]$89 Creating decoders for process `\axis_test.$proc$axis_test.v:16$86'. 1/1: $0$formal$axis_test.v:16$17_EN[0:0]$87 Creating decoders for process `\axis_test.$proc$axis_test.v:15$84'. 1/1: $0$formal$axis_test.v:15$16_EN[0:0]$85 Creating decoders for process `\axis_test.$proc$axis_test.v:14$82'. 1/1: $0$formal$axis_test.v:14$15_EN[0:0]$83 Creating decoders for process `\axis_test.$proc$axis_test.v:13$80'. 1/1: $0$formal$axis_test.v:13$14_EN[0:0]$81 Creating decoders for process `\axis_test.$proc$axis_test.v:7$79'. 1/1: $1\aresetn[0:0] Creating decoders for process `\axis_test.$proc$axis_test.v:6$78'. 1/1: $1\counter[31:0] Creating decoders for process `\axis_test.$proc$axis_test.v:11$24'. 1/22: $0\aresetn[0:0] 2/22: $0$formal$axis_test.v:13$14_EN[0:0]$27 3/22: $0$formal$axis_test.v:13$14_CHECK[0:0]$26 4/22: $0$formal$axis_test.v:14$15_EN[0:0]$28 5/22: $0$formal$axis_test.v:14$15_CHECK[0:0]$32 6/22: $0$formal$axis_test.v:15$16_EN[0:0]$30 7/22: $0$formal$axis_test.v:15$16_CHECK[0:0]$29 8/22: $0$formal$axis_test.v:16$17_EN[0:0]$25 9/22: $0$formal$axis_test.v:16$17_CHECK[0:0]$31 10/22: $0$formal$axis_test.v:17$18_EN[0:0]$34 11/22: $0$formal$axis_test.v:17$18_CHECK[0:0]$33 12/22: $0$formal$axis_test.v:18$19_EN[0:0]$36 13/22: $0$formal$axis_test.v:18$19_CHECK[0:0]$35 14/22: $0$formal$axis_test.v:19$20_EN[0:0]$38 15/22: $0$formal$axis_test.v:19$20_CHECK[0:0]$37 16/22: $0$formal$axis_test.v:20$21_EN[0:0]$40 17/22: $0$formal$axis_test.v:20$21_CHECK[0:0]$39 18/22: $0$formal$axis_test.v:21$22_EN[0:0]$42 19/22: $0$formal$axis_test.v:21$22_CHECK[0:0]$41 20/22: $0$formal$axis_test.v:22$23_EN[0:0]$44 21/22: $0$formal$axis_test.v:22$23_CHECK[0:0]$43 22/22: $0\counter[31:0] Creating decoders for process `\axis_master.$proc$axis_master.v:7$1'. 1/5: $2\state[31:0] 2/5: $1\state[31:0] 3/5: $0\state[31:0] 4/5: $0\tvalid[0:0] 5/5: $0\tdata[7:0] 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\axis_test.\aresetn' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$209' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$210' with positive edge clock. Creating register for signal `\axis_test.\counter' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$211' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$212' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$213' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$214' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$215' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$216' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$217' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$218' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$219' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$220' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$221' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$222' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$223' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$224' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$225' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$226' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$227' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$228' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$229' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$230' with positive edge clock. Creating register for signal `\axis_master.\tdata' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$231' with positive edge clock. Creating register for signal `\axis_master.\state' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$232' with positive edge clock. Creating register for signal `\axis_master.\tvalid' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$233' with positive edge clock. 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `axis_test.$proc$axis_test.v:22$98'. Removing empty process `axis_test.$proc$axis_test.v:21$96'. Removing empty process `axis_test.$proc$axis_test.v:20$94'. Removing empty process `axis_test.$proc$axis_test.v:19$92'. Removing empty process `axis_test.$proc$axis_test.v:18$90'. Removing empty process `axis_test.$proc$axis_test.v:17$88'. Removing empty process `axis_test.$proc$axis_test.v:16$86'. Removing empty process `axis_test.$proc$axis_test.v:15$84'. Removing empty process `axis_test.$proc$axis_test.v:14$82'. Removing empty process `axis_test.$proc$axis_test.v:13$80'. Removing empty process `axis_test.$proc$axis_test.v:7$79'. Removing empty process `axis_test.$proc$axis_test.v:6$78'. Found and cleaned up 11 empty switches in `\axis_test.$proc$axis_test.v:11$24'. Removing empty process `axis_test.$proc$axis_test.v:11$24'. Found and cleaned up 4 empty switches in `\axis_master.$proc$axis_master.v:7$1'. Removing empty process `axis_master.$proc$axis_master.v:7$1'. Cleaned up 15 empty switches. 5. Executing FLATTEN pass (flatten design). Using template axis_master for cells of type axis_master. No more expansions possible. Deleting now unused module axis_master. Removed 0 unused cells and 90 unused wires. 6. Executing SAT pass (solving SAT problems in the circuit). Setting up time step 1: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import set-constraint from init attribute: $formal$axis_test.v:13$14_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:14$15_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:15$16_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:16$17_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:17$18_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:18$19_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:19$20_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:20$21_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:21$22_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:22$23_EN = 1'0 Import set-constraint from init attribute: \aresetn = 1'0 Import set-constraint from init attribute: \counter = 0 Final init constraint equation: { \counter \aresetn $formal$axis_test.v:22$23_EN $formal$axis_test.v:21$22_EN $formal$axis_test.v:20$21_EN $formal$axis_test.v:19$20_EN $formal$axis_test.v:18$19_EN $formal$axis_test.v:17$18_EN $formal$axis_test.v:16$17_EN $formal$axis_test.v:15$16_EN $formal$axis_test.v:14$15_EN $formal$axis_test.v:13$14_EN } = 43'0000000000000000000000000000000000000000000 Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 2: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 3: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 4: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 5: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 6: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 7: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 8: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 9: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 10: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 11: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 12: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 13: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 14: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 15: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 16: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 17: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 18: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 19: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 20: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 21: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 22: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 23: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 24: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 25: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 26: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 27: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 28: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 29: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 30: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 31: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 32: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 33: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 34: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 35: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 36: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 37: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 38: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 39: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 40: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 41: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 42: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 43: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 44: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 45: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 46: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 47: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 48: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 49: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 50: Final constraint equation: { } = { } Imported 121 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Solving problem with 159344 variables and 442126 clauses.. SAT proof finished - model found: FAIL! ______ ___ ___ _ _ _ _ (_____ \ / __) / __) (_) | | | | _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | | | ____/ ___) _ \ / _ (_ __) (_ __|____ | | || ___ |/ _ |_| | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ |_| |_| \___/ \___/ |_| |_| \_____|_|\_)_____)\____|_| Time Signal Name Dec Hex Bin ---- ------------------------------------ ----------- --------- ----------------------------------- init $formal$axis_test.v:13$14_CHECK 0 0 0 init $formal$axis_test.v:13$14_EN 0 0 0 init $formal$axis_test.v:14$15_CHECK 0 0 0 init $formal$axis_test.v:14$15_EN 0 0 0 init $formal$axis_test.v:15$16_CHECK 0 0 0 init $formal$axis_test.v:15$16_EN 0 0 0 init $formal$axis_test.v:16$17_CHECK 0 0 0 init $formal$axis_test.v:16$17_EN 0 0 0 init $formal$axis_test.v:17$18_CHECK 0 0 0 init $formal$axis_test.v:17$18_EN 0 0 0 init $formal$axis_test.v:18$19_CHECK 0 0 0 init $formal$axis_test.v:18$19_EN 0 0 0 init $formal$axis_test.v:19$20_CHECK 0 0 0 init $formal$axis_test.v:19$20_EN 0 0 0 init $formal$axis_test.v:20$21_CHECK 0 0 0 init $formal$axis_test.v:20$21_EN 0 0 0 init $formal$axis_test.v:21$22_CHECK 0 0 0 init $formal$axis_test.v:21$22_EN 0 0 0 init $formal$axis_test.v:22$23_CHECK 0 0 0 init $formal$axis_test.v:22$23_EN 0 0 0 init \aresetn 0 0 0 init \counter 0 0 00000000000000000000000000000000 init \uut.state 0 0 00000000000000000000000000000000 init \uut.tdata 80 50 01010000 init \uut.tvalid 1 1 1 End of script. Logfile hash: f85fee5d76 CPU: user 1.91s system 0.12s, MEM: 119.82 MB total, 113.23 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 97% 1x sat (1 sec), 0% 1x clean (0 sec), ... mv axis_test.log_new axis_test.log make[3]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9/manual/PRESENTATION_ExOth' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20210815084447Z)#' PRESENTATION_ExOth/scrambler_p01.pdf PRESENTATION_ExOth/scrambler_p02.pdf + make -C PRESENTATION_Prog make[3]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys-config --exec --cxx --cxxflags -I../.. --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs my_cmd.cc: In member function ‘virtual void {anonymous}::MyPass::execute(std::vector >, Yosys::RTLIL::Design*)’: my_cmd.cc:17:26: warning: format ‘%zd’ expects argument of type ‘signed size_t’, but argument 3 has type ‘int’ [-Wformat=] 17 | log(" %s (%zd wires, %zd cells)\n", log_id(mod), | ~~^ | | | long int | %d 18 | GetSize(mod->wires()), GetSize(mod->cells())); | ~~~~~~~~~~~~~~~~~~~~~ | | | int my_cmd.cc:17:37: warning: format ‘%zd’ expects argument of type ‘signed size_t’, but argument 4 has type ‘int’ [-Wformat=] 17 | log(" %s (%zd wires, %zd cells)\n", log_id(mod), | ~~^ | | | long int | %d 18 | GetSize(mod->wires()), GetSize(mod->cells())); | ~~~~~~~~~~~~~~~~~~~~~ | | | int ../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v -- Parsing `absval_ref.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend: absval_ref.v Parsing Verilog input from `absval_ref.v' to AST representation. Generating RTLIL representation for module `\absval_ref'. Successfully finished Verilog frontend. -- Running command `my_cmd foo bar' -- Arguments to my_cmd: my_cmd foo bar Modules in current design: absval_ref (4 wires, 2 cells) End of script. Logfile hash: be47de2266 CPU: user 0.00s system 0.00s, MEM: 15.15 MB total, 9.70 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 95% 1x read_verilog (0 sec), 4% 1x my_cmd (0 sec) mv test0.log_new test0.log ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v -- Parsing `absval_ref.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend: absval_ref.v Parsing Verilog input from `absval_ref.v' to AST representation. Generating RTLIL representation for module `\absval_ref'. Successfully finished Verilog frontend. -- Running command `clean; test1; dump' -- Removed 0 unused cells and 1 unused wires. Name of this module: absval autoidx 6 module \absval wire width 4 $auto$my_cmd.cc:41:execute$3 wire width 4 output 2 \y wire width 4 input 1 \a cell $mux $auto$my_cmd.cc:43:execute$5 parameter \WIDTH 4 connect \Y \y connect \S \a [3] connect \B $auto$my_cmd.cc:41:execute$3 connect \A \a end cell $neg $auto$my_cmd.cc:42:execute$4 parameter \Y_WIDTH 4 parameter \A_WIDTH 4 parameter \A_SIGNED 1 connect \Y $auto$my_cmd.cc:41:execute$3 connect \A \a end end attribute \cells_not_processed 1 attribute \src "absval_ref.v:1" module \absval_ref attribute \src "absval_ref.v:2" wire width 4 $neg$absval_ref.v:2$1_Y attribute \src "absval_ref.v:1" wire width 4 input 1 \a attribute \src "absval_ref.v:1" wire width 4 output 2 \y attribute \src "absval_ref.v:2" cell $neg $neg$absval_ref.v:2$1 parameter \A_SIGNED 1 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \a connect \Y $neg$absval_ref.v:2$1_Y end attribute \src "absval_ref.v:2" cell $mux $ternary$absval_ref.v:2$2 parameter \WIDTH 4 connect \A \a connect \B $neg$absval_ref.v:2$1_Y connect \S \a [3] connect \Y \y end end End of script. Logfile hash: 41d715e711 CPU: user 0.01s system 0.00s, MEM: 15.15 MB total, 9.89 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 63% 1x clean (0 sec), 26% 1x read_verilog (0 sec), ... mv test1.log_new test1.log ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v -- Parsing `sigmap_test.v' using frontend `verilog' -- 1. Executing Verilog-2005 frontend: sigmap_test.v Parsing Verilog input from `sigmap_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. -- Running command `test2' -- 0 0 0 1 1 1 Mapped signal x: \a 2. Doing important stuff! Log message #0. Log message #1. Log message #2. Log message #3. Log message #4. Log message #5. Log message #6. Log message #7. Log message #8. Log message #9. End of script. Logfile hash: c613caebe8 CPU: user 0.01s system 0.00s, MEM: 15.15 MB total, 9.98 MB resident Yosys 0.9 (git sha1 1979e0b) Time spent: 80% 1x read_verilog (0 sec), 19% 1x test2 (0 sec) mv test2.log_new test2.log make[3]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9/manual/PRESENTATION_Prog' + set -ex + echo D:20210815084447Z D:20210815084447Z + pdflatex -shell-escape -halt-on-error '\pdfinfo{/CreationDate(D:20210815084447Z)/ModDate(D:20210815084447Z)}\input{presentation.tex}' This is pdfTeX, Version 3.14159265-2.6-1.40.21 (TeX Live 2020/Debian) (preloaded format=pdflatex) \write18 enabled. entering extended mode LaTeX2e <2020-10-01> patch level 4 L3 programming layer <2021-01-09> xparse <2020-03-03> (./presentation.tex (/usr/share/texlive/texmf-dist/tex/latex/beamer/beamer.cls Document Class: beamer 2020/11/26 v3.60 A class for typesetting presentations (/usr/share/texlive/texmf-dist/tex/latex/beamer/beamerbasemodes.sty (/usr/share/texlive/texmf-dist/tex/latex/etoolbox/etoolbox.sty) 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Transcript written on manual.log. + false + bibtex manual.aux This is BibTeX, Version 0.99d (TeX Live 2020/Debian) The top-level auxiliary file: manual.aux The style file: alphadin.bst Database file #1: literature.bib Warning--to sort, need author or key in Verilog2005 Warning--to sort, need author or key in VerilogSynth Warning--to sort, need author or key in VHDL Warning--to sort, need author or key in VHDLSynth Warning--to sort, need author or key in IP-XACT Warning--empty pages in Cummings00 Warning--empty pages in intersynthFdlBookChapter Warning--empty author in IP-XACT Warning--empty author in VerilogSynth Warning--empty author in Verilog2005 Warning--empty author in VHDLSynth Warning--empty author in VHDL (There were 12 warnings) + bibtex weblink.aux This is BibTeX, Version 0.99d (TeX Live 2020/Debian) The top-level auxiliary file: weblink.aux The style file: abbrv.bst Database file #1: weblinks.bib Warning--to sort, need author or key in C_to_Verilog Warning--to sort, need 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[176] [177 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [178 <./APPNOTE_010_Verilog_to_ BLIF.pdf>] [179 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [180 <./APPNOTE_011_Design _Investigation.pdf>] [181 <./APPNOTE_011_Design_Investigation.pdf>] [182 <./APP NOTE_011_Design_Investigation.pdf>] [183 <./APPNOTE_011_Design_Investigation.pd f>] [184 <./APPNOTE_011_Design_Investigation.pdf>] [185 <./APPNOTE_011_Design_I nvestigation.pdf>] [186 <./APPNOTE_011_Design_Investigation.pdf>] [187 <./APPNO TE_011_Design_Investigation.pdf>] [188 <./APPNOTE_011_Design_Investigation.pdf> ] [189 <./APPNOTE_012_Verilog_to_BTOR.pdf>] [190 <./APPNOTE_012_Verilog_to_BTOR .pdf>] [191 <./APPNOTE_012_Verilog_to_BTOR.pdf>]) (./manual.bbl [192]) (./weblink.bbl [193]) [194] (./manual.aux (./CHAPTER_Intro.aux) (./CHAPTER_Basics.aux) (./CHAPTER_Approach.aux) (./CHAPTER_Overview.aux) (./CHAPTER_CellLib.aux) (./CHAPTER_Prog.aux) (./CHAPTER_Verilog.aux) (./CHAPTER_Optimize.aux) (./CHAPTER_Techmap.aux) (./CHAPTER_Auxlibs.aux) (./CHAPTER_Auxprogs.aux) (./CHAPTER_Appnotes.aux)) LaTeX Font Warning: Some font shapes were not available, defaults substituted. LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc} {/usr/ share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/usr/share/tex mf/fonts/enc/dvips/lm/lm-mathit.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm. enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-d ist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}< /usr/share/texmf/fonts/type1/public/lm/lmri8.pfb> Output written on manual.pdf (194 pages, 1431874 bytes). Transcript written on manual.log. + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux CHAPTER_Appnotes.aux CHAPTER_Approach.aux CHAPTER_Auxlibs.aux CHAPTER_Auxprogs.aux CHAPTER_Basics.aux CHAPTER_CellLib.aux CHAPTER_Intro.aux CHAPTER_Optimize.aux CHAPTER_Overview.aux CHAPTER_Prog.aux CHAPTER_Techmap.aux CHAPTER_Verilog.aux PRESENTATION_ExAdv.aux PRESENTATION_ExOth.aux PRESENTATION_ExSyn.aux PRESENTATION_Intro.aux PRESENTATION_Prog.aux manual.aux presentation.aux weblink.aux manual.bbl weblink.bbl manual.blg weblink.blg + cmp autoloop.old autoloop.new + rm -f autoloop.old + rm -f autoloop.new + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' manual.pdf + mv -f manual.pdf.without_pdf_id manual.pdf make[2]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' make[1]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' dh_auto_test -i create-stamp debian/debhelper-build-stamp fakeroot debian/rules binary-indep PREFIX=/usr dh binary-indep --with=python3 dh_testroot -i dh_prep -i debian/rules override_dh_auto_install make[1]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' dh_auto_install make -j10 install DESTDIR=/build/yosys-RbN6Pn/yosys-0.9/debian/tmp AM_UPDATE_INFO_DIR=no "INSTALL=install --strip-program=true" make[2]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' [Makefile.conf] CONFIG := gcc mkdir -p /build/yosys-RbN6Pn/yosys-0.9/debian/tmp/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc /build/yosys-RbN6Pn/yosys-0.9/debian/tmp/usr/bin mkdir -p /build/yosys-RbN6Pn/yosys-0.9/debian/tmp/usr/share/yosys cp -r share/. /build/yosys-RbN6Pn/yosys-0.9/debian/tmp/usr/share/yosys/. make[2]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' chmod a-x debian/tmp/usr/share/yosys/achronix/speedster22i/cells*.v make[1]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' dh_install -i dh_installdocs -i dh_installchangelogs -i debian/rules override_dh_installman make[1]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' cd debian/man ; CHANGELOG_DATE="15 August 2021" ./genmanpages.sh dh_installman make[1]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' dh_python3 -i E: dh_python3 dh_python3:176: no package to act on (python3-foo or one with ${python3:Depends} in Depends) dh_perl -i dh_link -i dh_strip_nondeterminism -i debian/rules override_dh_compress make[1]: Entering directory '/build/yosys-RbN6Pn/yosys-0.9' dh_compress --exclude=.pdf make[1]: Leaving directory '/build/yosys-RbN6Pn/yosys-0.9' dh_fixperms -i dh_missing -i dh_installdeb -i dh_gencontrol -i dh_md5sums -i dh_builddeb -i dpkg-deb: building package 'yosys-doc' in '../yosys-doc_0.9-2_all.deb'. dpkg-genbuildinfo --build=all dpkg-genchanges --build=all >../yosys_0.9-2_all.changes dpkg-genchanges: info: binary-only arch-indep upload (source code and arch-specific packages not included) dpkg-source --after-build . dpkg-buildpackage: info: binary-only upload (no source included) I: running special hook: sync-out /build/yosys-RbN6Pn /tmp/yosys-0.9-22b8gom2u I: cleaning package lists and apt cache... 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