Input buildinfo: https://buildinfos.debian.net/buildinfo-pool/y/yosys/yosys_0.15-1_all.buildinfo Use metasnap for getting required timestamps New buildinfo file: /tmp/yosys-0.15-1hlyiqglp/yosys_0.15-1_all.buildinfo Get source package info: yosys=0.15-1 Source URL: http://snapshot.notset.fr/mr/package/yosys/0.15-1/srcfiles?fileinfo=1 env -i PATH=/usr/sbin:/usr/bin:/sbin:/bin TMPDIR=/tmp mmdebstrap --arch=amd64 --include=autoconf=2.71-2 automake=1:1.16.5-1.3 autopoint=0.21-6 autotools-dev=20220109.1 base-files=12.2 base-passwd=3.5.52 bash=5.1-6 berkeley-abc=1.01+20220306gitee22833+dfsg-1 binutils=2.38-3 binutils-common=2.38-3 binutils-x86-64-linux-gnu=2.38-3 bison=2:3.8.2+dfsg-1 bsdextrautils=2.37.3-1+b1 bsdutils=1:2.37.3-1+b1 build-essential=12.9 bzip2=1.0.8-5 coreutils=8.32-4.1 cpp=4:11.2.0-2 cpp-11=11.2.0-18 dash=0.5.11+git20210903+057cd650a4ed-8 debconf=1.5.79 debhelper=13.6 debianutils=5.7-0.1 dh-autoreconf=20 dh-python=5.20220215 dh-strip-nondeterminism=1.13.0-1 diffutils=1:3.7-5 dpkg=1.21.2 dpkg-dev=1.21.2 dwz=0.14-1 file=1:5.41-3 findutils=4.9.0-2 flex=2.6.4-8 fontconfig=2.13.1-4.4 fontconfig-config=2.13.1-4.4 fonts-dejavu-core=2.37-2 fonts-gfs-baskerville=1.1-6 fonts-gfs-porson=1.1-7 fonts-lmodern=2.005-1 g++=4:11.2.0-2 g++-11=11.2.0-18 gawk=1:5.1.0-1 gcc=4:11.2.0-2 gcc-11=11.2.0-18 gcc-11-base=11.2.0-18 gcc-12-base=12-20220319-1 gettext=0.21-6 gettext-base=0.21-6 graphviz=2.42.2-6+b2 grep=3.7-1 groff-base=1.22.4-8 gzip=1.10-4 hostname=3.23 init-system-helpers=1.62 intltool-debian=0.35.0+20060710.5 iverilog=11.0-1.1 libacl1=2.3.1-1 libann0=1.1.2+doc-7 libapache-pom-java=18-1 libarchive-zip-perl=1.68-1 libasan6=11.2.0-18 libatomic1=12-20220319-1 libattr1=1:2.5.1-1 libaudit-common=1:3.0.7-1 libaudit1=1:3.0.7-1+b1 libbinutils=2.38-3 libblkid1=2.37.3-1+b1 libbrotli1=1.0.9-2+b3 libbsd0=0.11.5-1+b1 libbz2-1.0=1.0.8-5 libc-bin=2.33-7 libc-dev-bin=2.33-7 libc6=2.33-7 libc6-dev=2.33-7 libcairo2=1.16.0-5 libcap-ng0=0.7.9-2.2+b1 libcap2=1:2.44-1 libcc1-0=12-20220319-1 libcdt5=2.42.2-6+b2 libcgraph6=2.42.2-6+b2 libcom-err2=1.46.5-2 libcommons-logging-java=1.2-2 libcommons-parent-java=43-1 libcrypt-dev=1:4.4.27-1.1 libcrypt1=1:4.4.27-1.1 libctf-nobfd0=2.38-3 libctf0=2.38-3 libdatrie1=0.2.13-2 libdb5.3=5.3.28+dfsg1-0.8 libdebconfclient0=0.261 libdebhelper-perl=13.6 libdeflate0=1.10-2 libdpkg-perl=1.21.2 libelf1=0.186-1 libexpat1=2.4.7-1 libffi-dev=3.4.2-4 libffi8=3.4.2-4 libfile-stripnondeterminism-perl=1.13.0-1 libfontbox-java=1:1.8.16-2 libfontconfig1=2.13.1-4.4 libfontenc1=1:1.1.4-1 libfreetype6=2.11.1+dfsg-1 libfribidi0=1.0.8-2 libgcc-11-dev=11.2.0-18 libgcc-s1=12-20220319-1 libgcrypt20=1.9.4-5 libgd3=2.3.0-2+b1 libgdbm-compat4=1.23-1 libgdbm6=1.23-1 libglib2.0-0=2.72.0-1 libgmp10=2:6.2.1+dfsg-3 libgomp1=12-20220319-1 libgpg-error0=1.43-3 libgraphite2-3=1.3.14-1 libgssapi-krb5-2=1.19.2-2+b1 libgts-0.7-5=0.7.6+darcs121130-5 libgvc6=2.42.2-6+b2 libgvpr2=2.42.2-6+b2 libharfbuzz0b=2.7.4-1 libice6=2:1.0.10-1 libicu67=67.1-7 libisl23=0.24-2 libitm1=12-20220319-1 libjbig0=2.1-3.1+b2 libjpeg62-turbo=1:2.1.2-1 libk5crypto3=1.19.2-2+b1 libkeyutils1=1.6.1-3 libkpathsea6=2021.20210626.59705-1 libkrb5-3=1.19.2-2+b1 libkrb5support0=1.19.2-2+b1 liblab-gamut1=2.42.2-6+b2 liblsan0=12-20220319-1 libltdl7=2.4.7-2 liblz4-1=1.9.3-2 liblzma5=5.2.5-2 libmagic-mgc=1:5.41-3 libmagic1=1:5.41-3 libmd0=1.0.4-1 libmount1=2.37.3-1+b1 libmpc3=1.2.1-2 libmpdec3=2.5.1-2 libmpfr6=4.1.0-3 libncurses-dev=6.3-2 libncurses6=6.3-2 libncursesw6=6.3-2 libnsl-dev=1.3.0-2 libnsl2=1.3.0-2 libpam-modules=1.4.0-11 libpam-modules-bin=1.4.0-11 libpam-runtime=1.4.0-11 libpam0g=1.4.0-11 libpango-1.0-0=1.50.6+ds-1 libpangocairo-1.0-0=1.50.6+ds-1 libpangoft2-1.0-0=1.50.6+ds-1 libpaper-utils=1.1.28+b1 libpaper1=1.1.28+b1 libpathplan4=2.42.2-6+b2 libpcre2-8-0=10.39-3 libpcre3=2:8.39-13 libpdfbox-java=1:1.8.16-2 libperl5.34=5.34.0-3 libpipeline1=1.5.5-1 libpixman-1-0=0.40.0-1 libpng16-16=1.6.37-3 libptexenc1=2021.20210626.59705-1 libpython3-stdlib=3.9.8-1 libpython3.9-minimal=3.9.12-1 libpython3.9-stdlib=3.9.12-1 libquadmath0=12-20220319-1 libreadline-dev=8.1.2-1 libreadline8=8.1.2-1 libseccomp2=2.5.3-2 libselinux1=3.3-1+b2 libsigsegv2=2.14-1 libsm6=2:1.2.3-1 libsmartcols1=2.37.3-1+b1 libsqlite3-0=3.38.1-1 libssl1.1=1.1.1n-1 libstdc++-11-dev=11.2.0-18 libstdc++6=12-20220319-1 libsub-override-perl=0.09-2 libsynctex2=2021.20210626.59705-1 libsystemd0=250.4-1 libtcl8.6=8.6.12+dfsg-1 libteckit0=2.5.11+ds1-1 libtexlua53=2021.20210626.59705-1 libtexluajit2=2021.20210626.59705-1 libthai-data=0.1.29-1 libthai0=0.1.29-1 libtiff5=4.3.0-6 libtinfo6=6.3-2 libtirpc-common=1.3.2-2 libtirpc-dev=1.3.2-2 libtirpc3=1.3.2-2 libtool=2.4.7-2 libtsan0=11.2.0-18 libubsan1=12-20220319-1 libuchardet0=0.0.7-1 libudev1=250.4-1 libunistring2=1.0-1 libuuid1=2.37.3-1+b1 libwebp7=1.2.2-2+b1 libx11-6=2:1.7.2-2+b1 libx11-data=2:1.7.2-2 libxau6=1:1.0.9-1 libxaw7=2:1.0.14-1 libxcb-render0=1.14-3 libxcb-shm0=1.14-3 libxcb1=1.14-3 libxdmcp6=1:1.1.2-3 libxext6=2:1.3.4-1 libxi6=2:1.8-1 libxml2=2.9.13+dfsg-1 libxmu6=2:1.1.3-3 libxpm4=1:3.5.12-1 libxrender1=1:0.9.10-1 libxt6=1:1.2.1-1 libzstd1=1.4.9+dfsg-1 libzzip-0-13=0.13.72+dfsg.1-1.1 linux-libc-dev=5.16.14-1 lmodern=2.005-1 login=1:4.11.1+dfsg1-2 lsb-base=11.1.0 m4=1.4.18-5 make=4.3-4.1 man-db=2.10.2-1 mawk=1.3.4.20200120-3+b1 media-types=7.0.0 ncurses-base=6.3-2 ncurses-bin=6.3-2 patch=2.7.6-7 perl=5.34.0-3 perl-base=5.34.0-3 perl-modules-5.34=5.34.0-3 pkg-config=0.29.2-1 po-debconf=1.0.21+nmu1 preview-latex-style=12.2-1 python3=3.9.8-1 python3-distutils=3.9.12-1 python3-lib2to3=3.9.12-1 python3-minimal=3.9.8-1 python3.9=3.9.12-1 python3.9-minimal=3.9.12-1 readline-common=8.1.2-1 rpcsvc-proto=1.4.2-4 sed=4.8-1 sensible-utils=0.0.17 sysvinit-utils=3.01-1 t1utils=1.41-4 tar=1.34+dfsg-1 tcl=8.6.11+1 tcl-dev=8.6.11+1 tcl8.6=8.6.12+dfsg-1 tcl8.6-dev=8.6.12+dfsg-1 tex-common=6.17 texlive-base=2021.20220204-1 texlive-bibtex-extra=2021.20220204-1 texlive-binaries=2021.20210626.59705-1 texlive-font-utils=2021.20220204-1 texlive-fonts-extra=2021.20220204-1 texlive-fonts-recommended=2021.20220204-1 texlive-lang-greek=2021.20220204-1 texlive-latex-base=2021.20220204-1 texlive-latex-extra=2021.20220204-1 texlive-latex-recommended=2021.20220204-1 texlive-pictures=2021.20220204-1 texlive-plain-generic=2021.20220204-1 texlive-publishers=2021.20220204-1 texlive-science=2021.20220204-1 txt2man=1.7.1-2 tzdata=2022a-1 ucf=3.0043 util-linux=2.37.3-1+b1 x11-common=1:7.7+23 xdg-utils=1.1.3-4.1 xfonts-encodings=1:1.0.4-2.1 xfonts-utils=1:7.7+6 xz-utils=5.2.5-2 zlib1g=1:1.2.11.dfsg-4 zlib1g-dev=1:1.2.11.dfsg-4 --variant=apt --aptopt=Acquire::Check-Valid-Until "false" --aptopt=Acquire::http::Dl-Limit "1000"; --aptopt=Acquire::https::Dl-Limit "1000"; --aptopt=Acquire::Retries "5"; --aptopt=APT::Get::allow-downgrades "true"; --keyring=/usr/share/keyrings/ --essential-hook=chroot "$1" sh -c "apt-get --yes install fakeroot util-linux" --essential-hook=copy-in /usr/share/keyrings/debian-archive-bullseye-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-security-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-stable.gpg /usr/share/keyrings/debian-archive-buster-automatic.gpg /usr/share/keyrings/debian-archive-buster-security-automatic.gpg /usr/share/keyrings/debian-archive-buster-stable.gpg /usr/share/keyrings/debian-archive-keyring.gpg /usr/share/keyrings/debian-archive-removed-keys.gpg /usr/share/keyrings/debian-archive-stretch-automatic.gpg /usr/share/keyrings/debian-archive-stretch-security-automatic.gpg /usr/share/keyrings/debian-archive-stretch-stable.gpg /usr/share/keyrings/debian-ports-archive-keyring-removed.gpg /usr/share/keyrings/debian-ports-archive-keyring.gpg /usr/share/keyrings/debian-keyring.gpg /etc/apt/trusted.gpg.d/ --essential-hook=chroot "$1" sh -c "rm /etc/apt/sources.list && echo 'deb http://snapshot.notset.fr/archive/debian/20220327T203647Z/ unstable main deb-src http://snapshot.notset.fr/archive/debian/20220327T203647Z/ unstable main deb http://snapshot.notset.fr/archive/debian/20220406T090904Z/ unstable main deb http://snapshot.notset.fr/archive/debian/20220324T214913Z/ unstable main' >> /etc/apt/sources.list && apt-get update" --customize-hook=chroot "$1" useradd --no-create-home -d /nonexistent -p "" builduser -s /bin/bash --customize-hook=chroot "$1" env sh -c "apt-get source --only-source -d yosys=0.15-1 && mkdir -p /build/yosys-cNltON && dpkg-source --no-check -x /*.dsc /build/yosys-cNltON/yosys-0.15 && chown -R builduser:builduser /build/yosys-cNltON" --customize-hook=chroot "$1" env --unset=TMPDIR runuser builduser -c "cd /build/yosys-cNltON/yosys-0.15 && env DEB_BUILD_OPTIONS="parallel=4" LC_ALL="C.UTF-8" LC_COLLATE="C.UTF-8" SOURCE_DATE_EPOCH="1648310123" DEB_BUILD_OPTIONS=nocheck dpkg-buildpackage -uc -a amd64 --build=all" --customize-hook=sync-out /build/yosys-cNltON /tmp/yosys-0.15-1hlyiqglp bookworm /dev/null deb http://snapshot.notset.fr/archive/debian/20220324T214913Z unstable main I: automatically chosen mode: root I: chroot architecture amd64 is equal to the host's architecture I: automatically chosen format: null I: using /tmp/mmdebstrap.QFu2xRen2I as tempdir I: running apt-get update... I: downloading packages with apt... I: extracting archives... I: installing essential packages... I: running --essential-hook in shell: sh -c 'chroot "$1" sh -c "apt-get --yes install fakeroot util-linux"' exec /tmp/mmdebstrap.QFu2xRen2I Reading package lists... Building dependency tree... util-linux is already the newest version (2.37.3-1+b1). The following NEW packages will be installed: fakeroot libfakeroot 0 upgraded, 2 newly installed, 0 to remove and 0 not upgraded. Need to get 135 kB of archives. After this operation, 406 kB of additional disk space will be used. Get:1 http://snapshot.notset.fr/archive/debian/20220324T214913Z unstable/main amd64 libfakeroot amd64 1.28-1 [48.2 kB] Get:2 http://snapshot.notset.fr/archive/debian/20220324T214913Z unstable/main amd64 fakeroot amd64 1.28-1 [87.2 kB] debconf: delaying package configuration, since apt-utils is not installed Fetched 135 kB in 0s (1073 kB/s) Selecting previously unselected package libfakeroot:amd64. (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 4702 files and directories currently installed.) Preparing to unpack .../libfakeroot_1.28-1_amd64.deb ... Unpacking libfakeroot:amd64 (1.28-1) ... Selecting previously unselected package fakeroot. Preparing to unpack .../fakeroot_1.28-1_amd64.deb ... Unpacking fakeroot (1.28-1) ... Setting up libfakeroot:amd64 (1.28-1) ... Setting up fakeroot (1.28-1) ... update-alternatives: using /usr/bin/fakeroot-sysv to provide /usr/bin/fakeroot (fakeroot) in auto mode Processing triggers for libc-bin (2.33-7) ... I: running special hook: copy-in /usr/share/keyrings/debian-archive-bullseye-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-security-automatic.gpg /usr/share/keyrings/debian-archive-bullseye-stable.gpg /usr/share/keyrings/debian-archive-buster-automatic.gpg /usr/share/keyrings/debian-archive-buster-security-automatic.gpg /usr/share/keyrings/debian-archive-buster-stable.gpg /usr/share/keyrings/debian-archive-keyring.gpg /usr/share/keyrings/debian-archive-removed-keys.gpg /usr/share/keyrings/debian-archive-stretch-automatic.gpg /usr/share/keyrings/debian-archive-stretch-security-automatic.gpg /usr/share/keyrings/debian-archive-stretch-stable.gpg /usr/share/keyrings/debian-ports-archive-keyring-removed.gpg /usr/share/keyrings/debian-ports-archive-keyring.gpg /usr/share/keyrings/debian-keyring.gpg /etc/apt/trusted.gpg.d/ I: running --essential-hook in shell: sh -c 'chroot "$1" sh -c "rm /etc/apt/sources.list && echo 'deb http://snapshot.notset.fr/archive/debian/20220327T203647Z/ unstable main deb-src http://snapshot.notset.fr/archive/debian/20220327T203647Z/ unstable main deb http://snapshot.notset.fr/archive/debian/20220406T090904Z/ unstable main deb http://snapshot.notset.fr/archive/debian/20220324T214913Z/ unstable main' >> /etc/apt/sources.list && apt-get update"' exec /tmp/mmdebstrap.QFu2xRen2I Get:1 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable InRelease [165 kB] Get:2 http://snapshot.notset.fr/archive/debian/20220406T090904Z unstable InRelease [165 kB] Hit:3 http://snapshot.notset.fr/archive/debian/20220324T214913Z unstable InRelease Ign:4 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main Sources Ign:5 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main amd64 Packages Ign:4 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main Sources Ign:5 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main amd64 Packages Ign:4 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main Sources Ign:5 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main amd64 Packages Get:4 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main Sources [12.8 MB] Get:5 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main amd64 Packages [12.4 MB] Ign:6 http://snapshot.notset.fr/archive/debian/20220406T090904Z unstable/main amd64 Packages Err:6 http://snapshot.notset.fr/archive/debian/20220406T090904Z unstable/main amd64 Packages 404 Not Found [IP: 10.13.0.253 80] Ign:6 http://snapshot.notset.fr/archive/debian/20220406T090904Z unstable/main amd64 Packages Get:6 http://snapshot.notset.fr/archive/debian/20220406T090904Z unstable/main amd64 Packages [12.4 MB] Fetched 37.9 MB in 30s (1245 kB/s) Reading package lists... I: installing remaining packages inside the chroot... I: running --customize-hook in shell: sh -c 'chroot "$1" useradd --no-create-home -d /nonexistent -p "" builduser -s /bin/bash' exec /tmp/mmdebstrap.QFu2xRen2I I: running --customize-hook in shell: sh -c 'chroot "$1" env sh -c "apt-get source --only-source -d yosys=0.15-1 && mkdir -p /build/yosys-cNltON && dpkg-source --no-check -x /*.dsc /build/yosys-cNltON/yosys-0.15 && chown -R builduser:builduser /build/yosys-cNltON"' exec /tmp/mmdebstrap.QFu2xRen2I Reading package lists... NOTICE: 'yosys' packaging is maintained in the 'Git' version control system at: https://salsa.debian.org/science-team/yosys.git Please use: git clone https://salsa.debian.org/science-team/yosys.git to retrieve the latest (possibly unreleased) updates to the package. Need to get 2264 kB of source archives. Get:1 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main yosys 0.15-1 (dsc) [2518 B] Get:2 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main yosys 0.15-1 (tar) [2245 kB] Get:3 http://snapshot.notset.fr/archive/debian/20220327T203647Z unstable/main yosys 0.15-1 (diff) [16.5 kB] Fetched 2264 kB in 2s (1116 kB/s) Download complete and in download only mode W: Download is performed unsandboxed as root as file 'yosys_0.15-1.dsc' couldn't be accessed by user '_apt'. - pkgAcquire::Run (13: Permission denied) dpkg-source: info: extracting yosys in /build/yosys-cNltON/yosys-0.15 dpkg-source: info: unpacking yosys_0.15.orig.tar.gz dpkg-source: info: unpacking yosys_0.15-1.debian.tar.xz dpkg-source: info: using patch list from debian/patches/series dpkg-source: info: applying switch-to-free-font.patch dpkg-source: info: applying kfreebsd-support.patch dpkg-source: info: applying 0007-Disable-pretty-build.patch dpkg-source: info: applying 0009-Some-spelling-errors-fixed.patch dpkg-source: info: applying 0010-Fix-reproducibility-of-PDF-documents-in-yosys-doc.patch dpkg-source: info: applying 0010-Fix-adding-of-sys.path-in-yosys-smtbmc.patch dpkg-source: info: applying 0011-Do-not-show-g-build-flags-in-Version-string.patch dpkg-source: info: applying 0012-Skip-non-deterministic-test-causing-random-FTBFS-on-.patch dpkg-source: info: applying 0014-Set-path-to-berkeley-abc-instead-of-relative-path-to.patch dpkg-source: info: applying 0017-Support-plugin-loading-from-libdir.patch I: running --customize-hook in shell: sh -c 'chroot "$1" env --unset=TMPDIR runuser builduser -c "cd /build/yosys-cNltON/yosys-0.15 && env DEB_BUILD_OPTIONS="parallel=4" LC_ALL="C.UTF-8" LC_COLLATE="C.UTF-8" SOURCE_DATE_EPOCH="1648310123" DEB_BUILD_OPTIONS=nocheck dpkg-buildpackage -uc -a amd64 --build=all"' exec /tmp/mmdebstrap.QFu2xRen2I dpkg-buildpackage: info: source package yosys dpkg-buildpackage: info: source version 0.15-1 dpkg-buildpackage: info: source distribution unstable dpkg-buildpackage: info: source changed by Daniel Gröber dpkg-source --before-build . debian/rules clean PREFIX=/usr dh clean --with=python3 debian/rules override_dh_auto_clean make[1]: Entering directory '/build/yosys-cNltON/yosys-0.15' dh_auto_clean -- GIT_REV=2156e20 ABCEXTERNAL="berkeley-abc" ABCPULL=0 STRIP=: make -j10 clean GIT_REV=2156e20 ABCEXTERNAL=berkeley-abc ABCPULL=0 STRIP=: make[2]: Entering directory '/build/yosys-cNltON/yosys-0.15' rm -rf share rm -rf kernel/*.pyh if test -d manual; then cd manual && sh clean.sh; fi find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f rm -f kernel/version_2156e20.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/qbfsat.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/gatemate/synth_gatemate.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/machxo2/synth_machxo2.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o frontends/rtlil/rtlil_parser.tab.cc frontends/rtlil/rtlil_parser.tab.hh frontends/rtlil/rtlil_parser.output frontends/rtlil/rtlil_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h techlibs/anlogic/brams_init_16.vh techlibs/anlogic/brams_init_9.vh techlibs/anlogic/brams_init_8.vh techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc techlibs/ecp5/bram_init_1_2_4.vh techlibs/ecp5/bram_init_9_18_36.vh techlibs/ecp5/bram_conn_1.vh techlibs/ecp5/bram_conn_2.vh techlibs/ecp5/bram_conn_4.vh techlibs/ecp5/bram_conn_9.vh techlibs/ecp5/bram_conn_18.vh techlibs/ecp5/bram_conn_36.vh techlibs/gowin/bram_init_16.vh techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh techlibs/xilinx/brams_init_9.vh techlibs/xilinx/brams_init_8.vh yosys yosys-config yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/binding.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/constids.inc share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/kernel/qcsat.h share/include/kernel/ff.h share/include/kernel/ffinit.h share/include/kernel/fstdata.h share/include/kernel/mem.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/fst/fstapi.h share/include/libs/sha1/sha1.h share/include/libs/json11/json11.hpp share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/frontends/ast/ast_binding.h share/include/frontends/blif/blifparse.h share/include/backends/rtlil/rtlil_backend.h share/include/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.h share/python3/smtio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/lutrams.txt share/anlogic/lutrams_map.v share/anlogic/lutram_init_16x4.vh share/anlogic/brams.txt share/anlogic/brams_map.v share/anlogic/brams_init_16.vh share/anlogic/brams_init_9.vh share/anlogic/brams_init_8.vh share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/mul2dsp.v share/abc9_model.v share/abc9_map.v share/abc9_unmap.v share/cmp2lcu.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/cells_counter_map.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/ecp5/cells_ff.vh share/ecp5/cells_io.vh share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/cells_bb.v share/ecp5/lutrams_map.v share/ecp5/lutrams.txt share/ecp5/brams_map.v share/ecp5/brams.txt share/ecp5/arith_map.v share/ecp5/latches_map.v share/ecp5/dsp_map.v share/ecp5/bram_init_1_2_4.vh share/ecp5/bram_init_9_18_36.vh share/ecp5/bram_conn_1.vh share/ecp5/bram_conn_2.vh share/ecp5/bram_conn_4.vh share/ecp5/bram_conn_9.vh share/ecp5/bram_conn_18.vh share/ecp5/bram_conn_36.vh share/efinix/cells_map.v share/efinix/arith_map.v share/efinix/cells_sim.v share/efinix/brams_map.v share/efinix/gbuf_map.v share/efinix/brams.txt share/gatemate/reg_map.v share/gatemate/mux_map.v share/gatemate/lut_map.v share/gatemate/mul_map.v share/gatemate/arith_map.v share/gatemate/cells_sim.v share/gatemate/cells_bb.v share/gatemate/brams_map.v share/gatemate/brams.txt share/gatemate/brams_init_20.vh share/gatemate/brams_init_40.vh share/gowin/cells_map.v share/gowin/cells_sim.v share/gowin/arith_map.v share/gowin/brams_map.v share/gowin/brams.txt share/gowin/lutrams_map.v share/gowin/lutrams.txt share/gowin/brams_init3.vh share/gowin/bram_init_16.vh share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/ff_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/dsp_map.v share/ice40/abc9_model.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams_m9k.txt share/intel/common/brams_map_m9k.v share/intel/common/ff_map.v share/intel/max10/cells_sim.v share/intel/cyclone10lp/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/cyclone10lp/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_model.v share/intel_alm/common/alm_map.v share/intel_alm/common/alm_sim.v share/intel_alm/common/arith_alm_map.v share/intel_alm/common/dff_map.v share/intel_alm/common/dff_sim.v share/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_map.v share/intel_alm/common/mem_sim.v share/intel_alm/common/misc_sim.v share/intel_alm/cyclonev/cells_sim.v share/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k_map.v share/intel_alm/common/lutram_mlab.txt share/intel_alm/common/megafunction_bb.v share/intel_alm/common/quartus_rename.v share/machxo2/cells_map.v share/machxo2/cells_sim.v share/nexus/cells_map.v share/nexus/cells_sim.v share/nexus/parse_init.vh share/nexus/cells_xtra.v share/nexus/lutrams_map.v share/nexus/lutrams.txt share/nexus/brams_init.vh share/nexus/brams_map.v share/nexus/brams.txt share/nexus/lrams_init.vh share/nexus/lrams_map.v share/nexus/lrams.txt share/nexus/arith_map.v share/nexus/latches_map.v share/nexus/dsp_map.v share/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_lut_map.v share/quicklogic/pp3_latches_map.v share/quicklogic/pp3_cells_map.v share/quicklogic/cells_sim.v share/quicklogic/lut_sim.v share/quicklogic/pp3_cells_sim.v share/quicklogic/abc9_model.v share/quicklogic/abc9_map.v share/quicklogic/abc9_unmap.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/xc2v_brams.txt share/xilinx/xc2v_brams_map.v share/xilinx/xc3sa_brams.txt share/xilinx/xc3sda_brams.txt share/xilinx/xc6s_brams.txt share/xilinx/xc6s_brams_map.v share/xilinx/xc7_xcu_brams.txt share/xilinx/xc7_brams_map.v share/xilinx/xcu_brams_map.v share/xilinx/xcup_urams.txt share/xilinx/xcup_urams_map.v share/xilinx/lut4_lutrams.txt share/xilinx/lut6_lutrams.txt share/xilinx/lutrams_map.v share/xilinx/arith_map.v share/xilinx/ff_map.v share/xilinx/lut_map.v share/xilinx/mux_map.v share/xilinx/xc3s_mult_map.v share/xilinx/xc3sda_dsp_map.v share/xilinx/xc6s_dsp_map.v share/xilinx/xc4v_dsp_map.v share/xilinx/xc5v_dsp_map.v share/xilinx/xc7_dsp_map.v share/xilinx/xcu_dsp_map.v share/xilinx/abc9_model.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh share/xilinx/brams_init_9.vh share/xilinx/brams_init_8.vh passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h passes/techmap/filterlib.o techlibs/anlogic/brams_init.mk techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/gowin/brams_init.mk techlibs/ice40/brams_init.mk techlibs/xilinx/brams_init.mk .cc rm -f kernel/version_*.o kernel/version_*.cc rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff rm -f tests/tools/cmp_tbdata make[2]: Leaving directory '/build/yosys-cNltON/yosys-0.15' rm -f debian/man/*.1 rm -f Makefile.conf make[1]: Leaving directory '/build/yosys-cNltON/yosys-0.15' dh_clean debian/rules binary-indep PREFIX=/usr dh binary-indep --with=python3 dh_update_autotools_config -i dh_autoreconf -i debian/rules override_dh_auto_configure make[1]: Entering directory '/build/yosys-cNltON/yosys-0.15' make config-gcc make[2]: Entering directory '/build/yosys-cNltON/yosys-0.15' rm -rf share rm -rf kernel/*.pyh if test -d manual; then cd manual && sh clean.sh; fi find ./ -name '*.aux' | xargs rm -f find ./ -name '*.bbl' | xargs rm -f find ./ -name '*.blg' | xargs rm -f find ./ -name '*.idx' | xargs rm -f find ./ -name '*.log' | xargs rm -f find ./ -name '*.out' | xargs rm -f find ./ -name '*.pdf' | xargs rm -f find ./ -name '*.toc' | xargs rm -f find ./ -name '*.snm' | xargs rm -f find ./ -name '*.nav' | xargs rm -f find ./ -name '*.vrb' | xargs rm -f find ./ -name '*.ok' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.so' | xargs rm -f find ./CHAPTER_Prog/ -name 'stubnets.d' | xargs rm -f find ./CHAPTER_Prog/ -name '*.log' | xargs rm -f find ./PRESENTATION_ExAdv/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExOth/ -name '*.dot' | xargs rm -f find ./PRESENTATION_ExSyn/ -name '*.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_00.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_01.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_02.dot' | xargs rm -f find ./PRESENTATION_Intro/ -name 'counter_03.dot' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.so' | xargs rm -f find ./PRESENTATION_Prog/ -name 'my_cmd.d' | xargs rm -f rm -f kernel/version_UNKNOWN.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/qbfsat.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/gatemate/synth_gatemate.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/machxo2/synth_machxo2.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o frontends/rtlil/rtlil_parser.tab.cc frontends/rtlil/rtlil_parser.tab.hh frontends/rtlil/rtlil_parser.output frontends/rtlil/rtlil_lexer.cc frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh frontends/verilog/verilog_parser.output frontends/verilog/verilog_lexer.cc passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h techlibs/anlogic/brams_init_16.vh techlibs/anlogic/brams_init_9.vh techlibs/anlogic/brams_init_8.vh techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc techlibs/ecp5/bram_init_1_2_4.vh techlibs/ecp5/bram_init_9_18_36.vh techlibs/ecp5/bram_conn_1.vh techlibs/ecp5/bram_conn_2.vh techlibs/ecp5/bram_conn_4.vh techlibs/ecp5/bram_conn_9.vh techlibs/ecp5/bram_conn_18.vh techlibs/ecp5/bram_conn_36.vh techlibs/gowin/bram_init_16.vh techlibs/ice40/brams_init1.vh techlibs/ice40/brams_init2.vh techlibs/ice40/brams_init3.vh techlibs/xilinx/brams_init_36.vh techlibs/xilinx/brams_init_32.vh techlibs/xilinx/brams_init_18.vh techlibs/xilinx/brams_init_16.vh techlibs/xilinx/brams_init_9.vh techlibs/xilinx/brams_init_8.vh yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc share/include/kernel/yosys.h share/include/kernel/hashlib.h share/include/kernel/log.h share/include/kernel/rtlil.h share/include/kernel/binding.h share/include/kernel/register.h share/include/kernel/celltypes.h share/include/kernel/celledges.h share/include/kernel/consteval.h share/include/kernel/constids.inc share/include/kernel/sigtools.h share/include/kernel/modtools.h share/include/kernel/macc.h share/include/kernel/utils.h share/include/kernel/satgen.h share/include/kernel/qcsat.h share/include/kernel/ff.h share/include/kernel/ffinit.h share/include/kernel/fstdata.h share/include/kernel/mem.h share/include/libs/ezsat/ezsat.h share/include/libs/ezsat/ezminisat.h share/include/libs/fst/fstapi.h share/include/libs/sha1/sha1.h share/include/libs/json11/json11.hpp share/include/passes/fsm/fsmdata.h share/include/frontends/ast/ast.h share/include/frontends/ast/ast_binding.h share/include/frontends/blif/blifparse.h share/include/backends/rtlil/rtlil_backend.h share/include/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.h share/python3/smtio.py share/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_map.v share/anlogic/cells_map.v share/anlogic/arith_map.v share/anlogic/cells_sim.v share/anlogic/eagle_bb.v share/anlogic/lutrams.txt share/anlogic/lutrams_map.v share/anlogic/lutram_init_16x4.vh share/anlogic/brams.txt share/anlogic/brams_map.v share/anlogic/brams_init_16.vh share/anlogic/brams_init_9.vh share/anlogic/brams_init_8.vh share/simlib.v share/simcells.v share/techmap.v share/pmux2mux.v share/adff2dff.v share/dff2ff.v share/gate2lut.v share/cmp2lut.v share/cells.lib share/mul2dsp.v share/abc9_model.v share/abc9_map.v share/abc9_unmap.v share/cmp2lcu.v share/coolrunner2/cells_latch.v share/coolrunner2/cells_sim.v share/coolrunner2/cells_counter_map.v share/coolrunner2/tff_extract.v share/coolrunner2/xc2_dff.lib share/ecp5/cells_ff.vh share/ecp5/cells_io.vh share/ecp5/cells_map.v share/ecp5/cells_sim.v share/ecp5/cells_bb.v share/ecp5/lutrams_map.v share/ecp5/lutrams.txt share/ecp5/brams_map.v share/ecp5/brams.txt share/ecp5/arith_map.v share/ecp5/latches_map.v share/ecp5/dsp_map.v share/ecp5/bram_init_1_2_4.vh share/ecp5/bram_init_9_18_36.vh share/ecp5/bram_conn_1.vh share/ecp5/bram_conn_2.vh share/ecp5/bram_conn_4.vh share/ecp5/bram_conn_9.vh share/ecp5/bram_conn_18.vh share/ecp5/bram_conn_36.vh share/efinix/cells_map.v share/efinix/arith_map.v share/efinix/cells_sim.v share/efinix/brams_map.v share/efinix/gbuf_map.v share/efinix/brams.txt share/gatemate/reg_map.v share/gatemate/mux_map.v share/gatemate/lut_map.v share/gatemate/mul_map.v share/gatemate/arith_map.v share/gatemate/cells_sim.v share/gatemate/cells_bb.v share/gatemate/brams_map.v share/gatemate/brams.txt share/gatemate/brams_init_20.vh share/gatemate/brams_init_40.vh share/gowin/cells_map.v share/gowin/cells_sim.v share/gowin/arith_map.v share/gowin/brams_map.v share/gowin/brams.txt share/gowin/lutrams_map.v share/gowin/lutrams.txt share/gowin/brams_init3.vh share/gowin/bram_init_16.vh share/greenpak4/cells_blackbox.v share/greenpak4/cells_latch.v share/greenpak4/cells_map.v share/greenpak4/cells_sim.v share/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_wip.v share/greenpak4/gp_dff.lib share/ice40/arith_map.v share/ice40/cells_map.v share/ice40/ff_map.v share/ice40/cells_sim.v share/ice40/latches_map.v share/ice40/brams.txt share/ice40/brams_map.v share/ice40/dsp_map.v share/ice40/abc9_model.v share/ice40/brams_init1.vh share/ice40/brams_init2.vh share/ice40/brams_init3.vh share/intel/common/m9k_bb.v share/intel/common/altpll_bb.v share/intel/common/brams_m9k.txt share/intel/common/brams_map_m9k.v share/intel/common/ff_map.v share/intel/max10/cells_sim.v share/intel/cyclone10lp/cells_sim.v share/intel/cycloneiv/cells_sim.v share/intel/cycloneive/cells_sim.v share/intel/max10/cells_map.v share/intel/cyclone10lp/cells_map.v share/intel/cycloneiv/cells_map.v share/intel/cycloneive/cells_map.v share/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_model.v share/intel_alm/common/alm_map.v share/intel_alm/common/alm_sim.v share/intel_alm/common/arith_alm_map.v share/intel_alm/common/dff_map.v share/intel_alm/common/dff_sim.v share/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_map.v share/intel_alm/common/mem_sim.v share/intel_alm/common/misc_sim.v share/intel_alm/cyclonev/cells_sim.v share/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k_map.v share/intel_alm/common/lutram_mlab.txt share/intel_alm/common/megafunction_bb.v share/intel_alm/common/quartus_rename.v share/machxo2/cells_map.v share/machxo2/cells_sim.v share/nexus/cells_map.v share/nexus/cells_sim.v share/nexus/parse_init.vh share/nexus/cells_xtra.v share/nexus/lutrams_map.v share/nexus/lutrams.txt share/nexus/brams_init.vh share/nexus/brams_map.v share/nexus/brams.txt share/nexus/lrams_init.vh share/nexus/lrams_map.v share/nexus/lrams.txt share/nexus/arith_map.v share/nexus/latches_map.v share/nexus/dsp_map.v share/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_lut_map.v share/quicklogic/pp3_latches_map.v share/quicklogic/pp3_cells_map.v share/quicklogic/cells_sim.v share/quicklogic/lut_sim.v share/quicklogic/pp3_cells_sim.v share/quicklogic/abc9_model.v share/quicklogic/abc9_map.v share/quicklogic/abc9_unmap.v share/sf2/arith_map.v share/sf2/cells_map.v share/sf2/cells_sim.v share/xilinx/cells_map.v share/xilinx/cells_sim.v share/xilinx/cells_xtra.v share/xilinx/xc2v_brams.txt share/xilinx/xc2v_brams_map.v share/xilinx/xc3sa_brams.txt share/xilinx/xc3sda_brams.txt share/xilinx/xc6s_brams.txt share/xilinx/xc6s_brams_map.v share/xilinx/xc7_xcu_brams.txt share/xilinx/xc7_brams_map.v share/xilinx/xcu_brams_map.v share/xilinx/xcup_urams.txt share/xilinx/xcup_urams_map.v share/xilinx/lut4_lutrams.txt share/xilinx/lut6_lutrams.txt share/xilinx/lutrams_map.v share/xilinx/arith_map.v share/xilinx/ff_map.v share/xilinx/lut_map.v share/xilinx/mux_map.v share/xilinx/xc3s_mult_map.v share/xilinx/xc3sda_dsp_map.v share/xilinx/xc6s_dsp_map.v share/xilinx/xc4v_dsp_map.v share/xilinx/xc5v_dsp_map.v share/xilinx/xc7_dsp_map.v share/xilinx/xcu_dsp_map.v share/xilinx/abc9_model.v share/xilinx/brams_init_36.vh share/xilinx/brams_init_32.vh share/xilinx/brams_init_18.vh share/xilinx/brams_init_16.vh share/xilinx/brams_init_9.vh share/xilinx/brams_init_8.vh passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_wrapcarry_pm.h passes/pmgen/xilinx_dsp_pm.h passes/pmgen/xilinx_dsp48a_pm.h passes/pmgen/xilinx_dsp_CREG_pm.h passes/pmgen/xilinx_dsp_cascade_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h passes/techmap/filterlib.o techlibs/anlogic/brams_init.mk techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/gowin/brams_init.mk techlibs/ice40/brams_init.mk techlibs/xilinx/brams_init.mk .cc rm -f kernel/version_*.o kernel/version_*.cc rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log rm -rf tests/simple/*.out tests/simple/*.log rm -rf tests/memories/*.out tests/memories/*.log tests/memories/*.dmp rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_* rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff rm -f tests/tools/cmp_tbdata echo 'CONFIG := gcc' > Makefile.conf make[2]: Leaving directory '/build/yosys-cNltON/yosys-0.15' make[1]: Leaving directory '/build/yosys-cNltON/yosys-0.15' debian/rules override_dh_auto_build-indep make[1]: Entering directory '/build/yosys-cNltON/yosys-0.15' sed -i 's/REPLACEWITHDATE/March 26, 2022/' manual/presentation.tex PDF_DATE=D:20220326155523Z dh_auto_build -- GIT_REV=2156e20 ABCEXTERNAL="berkeley-abc" ABCPULL=0 STRIP=: all manual make -j10 "INSTALL=install --strip-program=true" GIT_REV=2156e20 ABCEXTERNAL=berkeley-abc ABCPULL=0 STRIP=: all manual make[2]: Entering directory '/build/yosys-cNltON/yosys-0.15' [Makefile.conf] CONFIG := gcc rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.15 (git sha1 2156e20)\"; }" > kernel/version_2156e20.cc mkdir -p kernel/ mkdir -p techlibs/common gcc -o kernel/driver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new mkdir -p techlibs/common python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new mkdir -p kernel/ gcc -o kernel/rtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc mkdir -p kernel/ gcc -o kernel/log.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc mkdir -p kernel/ gcc -o kernel/calc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc mkdir -p kernel/ mkdir -p kernel/ gcc -o kernel/yosys.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' -DYOSYS_DATDIR='"/usr/share/yosys"' -DYOSYS_PROGRAM_PREFIX='""' kernel/yosys.cc gcc -o kernel/binding.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/binding.cc mkdir -p kernel/ mkdir -p kernel/ gcc -o kernel/cellaigs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc gcc -o kernel/celledges.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc mkdir -p kernel/ gcc -o kernel/satgen.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/satgen.cc mkdir -p kernel/ gcc -o kernel/qcsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/qcsat.cc mkdir -p kernel/ gcc -o kernel/mem.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/mem.cc mkdir -p kernel/ gcc -o kernel/ffmerge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ffmerge.cc mkdir -p kernel/ gcc -o kernel/ff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ff.cc mkdir -p kernel/ gcc -o kernel/fstdata.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/fstdata.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigIntegerAlgorithms.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerAlgorithms.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigInteger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigInteger.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigIntegerUtils.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerUtils.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsigned.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsigned.cc mkdir -p libs/bigint/ gcc -o libs/bigint/BigUnsignedInABase.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsignedInABase.cc mkdir -p libs/sha1/ gcc -o libs/sha1/sha1.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp mkdir -p libs/json11/ gcc -o libs/json11/json11.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/json11/json11.cpp mkdir -p libs/subcircuit/ gcc -o libs/subcircuit/subcircuit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc kernel/satgen.cc: In member function ‘bool Yosys::SatGen::importCell(Yosys::RTLIL::Cell*, int)’: kernel/satgen.cc:1237:67: warning: ‘undef_srst’ may be used uninitialized in this function [-Wmaybe-uninitialized] 1237 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1223:67: warning: ‘undef_ce’ may be used uninitialized in this function [-Wmaybe-uninitialized] 1223 | std::tie(d, undef_d) = mux(ce, undef_ce, d, undef_d, old_q, undef_old_q); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ kernel/satgen.cc:1209:67: warning: ‘undef_srst’ may be used uninitialized in this function [-Wmaybe-uninitialized] 1209 | std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d); | ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc mkdir -p libs/ezsat/ gcc -o libs/ezsat/ezminisat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezminisat.cc mkdir -p libs/minisat/ gcc -o libs/minisat/Options.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Options.cc mkdir -p libs/minisat/ gcc -o libs/minisat/SimpSolver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/SimpSolver.cc mkdir -p libs/minisat/ gcc -o libs/minisat/Solver.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Solver.cc mkdir -p libs/minisat/ gcc -o libs/minisat/System.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/System.cc In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h: In instantiation of ‘void Minisat::vec::capacity(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’: libs/minisat/Vec.h:119:13: required from ‘void Minisat::vec::growTo(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’ libs/minisat/IntMap.h:48:58: required from ‘void Minisat::IntMap::reserve(K) [with K = int; V = Minisat::vec; MkIndex = Minisat::MkIndexDefault]’ libs/minisat/SolverTypes.h:338:49: required from ‘void Minisat::OccLists::init(const K&) [with K = int; Vec = Minisat::vec; Deleted = Minisat::SimpSolver::ClauseDeleted; MkIndex = Minisat::MkIndexDefault]’ libs/minisat/SimpSolver.cc:92:26: required from here libs/minisat/Vec.h:103:33: warning: ‘void* realloc(void*, size_t)’ moving an object of non-trivially copyable type ‘class Minisat::vec’; use ‘new’ and ‘delete’ instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Sort.h:24, from libs/minisat/SimpSolver.cc:27: libs/minisat/Vec.h:39:7: note: ‘class Minisat::vec’ declared here 39 | class vec { | ^~~ mkdir -p libs/fst/ gcc -o libs/fst/fstapi.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fstapi.cc In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h: In instantiation of ‘void Minisat::vec::capacity(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’: libs/minisat/Vec.h:119:13: required from ‘void Minisat::vec::growTo(Minisat::vec::Size) [with T = Minisat::vec; _Size = int; Minisat::vec::Size = int]’ libs/minisat/IntMap.h:48:58: required from ‘void Minisat::IntMap::reserve(K) [with K = Minisat::Lit; V = Minisat::vec; MkIndex = Minisat::MkIndexLit]’ libs/minisat/SolverTypes.h:338:49: required from ‘void Minisat::OccLists::init(const K&) [with K = Minisat::Lit; Vec = Minisat::vec; Deleted = Minisat::Solver::WatcherDeleted; MkIndex = Minisat::MkIndexLit]’ libs/minisat/Solver.cc:134:19: required from here libs/minisat/Vec.h:103:33: warning: ‘void* realloc(void*, size_t)’ moving an object of non-trivially copyable type ‘class Minisat::vec’; use ‘new’ and ‘delete’ instead [-Wclass-memaccess] 103 | || (((data = (T*)::realloc(data, (cap += add) * sizeof(T))) == NULL) && errno == ENOMEM) ) | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from libs/minisat/Alg.h:24, from libs/minisat/Solver.cc:29: libs/minisat/Vec.h:39:7: note: ‘class Minisat::vec’ declared here 39 | class vec { | ^~~ mkdir -p libs/fst/ gcc -o libs/fst/fastlz.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fastlz.cc mkdir -p libs/fst/ gcc -o libs/fst/lz4.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/lz4.cc mkdir -p frontends/aiger/ gcc -o frontends/aiger/aigerparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/aiger/aigerparse.cc mkdir -p frontends/ast/ gcc -o frontends/ast/ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast.cc mkdir -p frontends/ast/ gcc -o frontends/ast/simplify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/simplify.cc mkdir -p frontends/ast/ gcc -o frontends/ast/genrtlil.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/genrtlil.cc mkdir -p frontends/ast/ gcc -o frontends/ast/dpicall.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/dpicall.cc mkdir -p frontends/ast/ gcc -o frontends/ast/ast_binding.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast_binding.cc mkdir -p frontends/blif/ gcc -o frontends/blif/blifparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/blif/blifparse.cc mkdir -p frontends/json/ gcc -o frontends/json/jsonparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/json/jsonparse.cc mkdir -p frontends/liberty/ gcc -o frontends/liberty/liberty.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/liberty/liberty.cc mkdir -p frontends/rpc/ gcc -o frontends/rpc/rpc_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rpc/rpc_frontend.cc mkdir -p frontends/rtlil/ bison -o frontends/rtlil/rtlil_parser.tab.cc -d -r all -b frontends/rtlil/rtlil_parser frontends/rtlil/rtlil_parser.y mkdir -p frontends/rtlil/ flex -o frontends/rtlil/rtlil_lexer.cc frontends/rtlil/rtlil_lexer.l mkdir -p frontends/rtlil/ gcc -o frontends/rtlil/rtlil_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_frontend.cc mkdir -p frontends/verific/ gcc -o frontends/verific/verific.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verific/verific.cc mkdir -p frontends/verilog/ bison -Wall -Werror -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y mkdir -p frontends/verilog/ gcc -o frontends/verilog/preproc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_frontend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc mkdir -p frontends/verilog/ gcc -o frontends/verilog/const2ast.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc mkdir -p passes/cmds/ gcc -o passes/cmds/exec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/exec.cc mkdir -p passes/cmds/ gcc -o passes/cmds/add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/add.cc mkdir -p passes/cmds/ gcc -o passes/cmds/delete.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/delete.cc mkdir -p passes/cmds/ gcc -o passes/cmds/design.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/design.cc mkdir -p passes/cmds/ gcc -o passes/cmds/select.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/select.cc mkdir -p passes/cmds/ gcc -o passes/cmds/show.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/show.cc mkdir -p passes/cmds/ gcc -o passes/cmds/rename.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/rename.cc mkdir -p passes/cmds/ gcc -o passes/cmds/autoname.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/autoname.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connect.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scatter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scatter.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setundef.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setundef.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splitnets.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitnets.cc mkdir -p passes/cmds/ gcc -o passes/cmds/stat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/stat.cc mkdir -p passes/cmds/ gcc -o passes/cmds/setattr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setattr.cc mkdir -p passes/cmds/ gcc -o passes/cmds/copy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/copy.cc mkdir -p passes/cmds/ gcc -o passes/cmds/splice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splice.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scc.cc mkdir -p passes/cmds/ gcc -o passes/cmds/glift.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/glift.cc mkdir -p passes/cmds/ gcc -o passes/cmds/torder.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/torder.cc mkdir -p passes/cmds/ gcc -o passes/cmds/logcmd.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logcmd.cc mkdir -p passes/cmds/ gcc -o passes/cmds/tee.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/tee.cc mkdir -p passes/cmds/ gcc -o passes/cmds/write_file.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/write_file.cc mkdir -p passes/cmds/ gcc -o passes/cmds/connwrappers.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connwrappers.cc mkdir -p passes/cmds/ gcc -o passes/cmds/cover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/cover.cc mkdir -p passes/cmds/ gcc -o passes/cmds/trace.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/trace.cc mkdir -p passes/cmds/ gcc -o passes/cmds/plugin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/plugin.cc mkdir -p passes/cmds/ gcc -o passes/cmds/check.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/check.cc mkdir -p passes/cmds/ gcc -o passes/cmds/qwp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/qwp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/edgetypes.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/edgetypes.cc mkdir -p passes/cmds/ gcc -o passes/cmds/portlist.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/portlist.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chformal.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chformal.cc mkdir -p passes/cmds/ gcc -o passes/cmds/chtype.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chtype.cc mkdir -p passes/cmds/ gcc -o passes/cmds/blackbox.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/blackbox.cc mkdir -p passes/cmds/ gcc -o passes/cmds/ltp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/ltp.cc mkdir -p passes/cmds/ gcc -o passes/cmds/bugpoint.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/bugpoint.cc mkdir -p passes/cmds/ gcc -o passes/cmds/scratchpad.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scratchpad.cc mkdir -p passes/cmds/ gcc -o passes/cmds/logger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logger.cc mkdir -p passes/cmds/ gcc -o passes/cmds/printattrs.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/printattrs.cc mkdir -p passes/cmds/ gcc -o passes/cmds/sta.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/sta.cc mkdir -p passes/cmds/ gcc -o passes/cmds/clean_zerowidth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/clean_zerowidth.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_make.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_make.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_miter.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_simple.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_simple.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_status.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_status.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_add.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_add.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_remove.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_remove.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_induct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_induct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_struct.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_struct.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_purge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_purge.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_mark.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_mark.cc mkdir -p passes/equiv/ gcc -o passes/equiv/equiv_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_detect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_detect.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_extract.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_opt.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_expand.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_expand.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_recode.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_recode.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_info.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_info.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_export.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_export.cc mkdir -p passes/fsm/ gcc -o passes/fsm/fsm_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_map.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/hierarchy.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/hierarchy.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/uniquify.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/uniquify.cc mkdir -p passes/hierarchy/ gcc -o passes/hierarchy/submod.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/submod.cc mkdir -p passes/memory/ gcc -o passes/memory/memory.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_dff.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_share.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_collect.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_collect.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_unpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_unpack.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_bram.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bram.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_map.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_map.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_memx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_memx.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_nordff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_nordff.cc mkdir -p passes/memory/ gcc -o passes/memory/memory_narrow.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_narrow.cc mkdir -p passes/opt/ gcc -o passes/opt/opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_merge.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_merge.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem_feedback.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_feedback.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem_priority.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_priority.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_mem_widen.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_widen.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_muxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_muxtree.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_reduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_dff.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_share.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_clean.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_expr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_expr.cc mkdir -p passes/opt/ gcc -o passes/opt/share.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/share.cc mkdir -p passes/opt/ gcc -o passes/opt/wreduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/wreduce.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_demorgan.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_demorgan.cc mkdir -p passes/opt/ gcc -o passes/opt/rmports.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/rmports.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_lut.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut.cc mkdir -p passes/opt/ gcc -o passes/opt/opt_lut_ins.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut_ins.cc mkdir -p passes/opt/ gcc -o passes/opt/pmux2shiftx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/pmux2shiftx.cc mkdir -p passes/opt/ gcc -o passes/opt/muxpack.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/muxpack.cc mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/test_pmgen_pm.h -p test_pmgen passes/pmgen/test_pmgen.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_dsp_pm.h -p ice40_dsp passes/pmgen/ice40_dsp.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/peepopt_pm.h -p peepopt passes/pmgen/peepopt_shiftmul.pmg passes/pmgen/peepopt_muldiv.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_srl_pm.h -p xilinx_srl passes/pmgen/xilinx_srl.pmg mkdir -p passes/pmgen/ gcc -o passes/pmgen/ice40_dsp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_dsp.cc mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_wrapcarry_pm.h -p ice40_wrapcarry passes/pmgen/ice40_wrapcarry.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_pm.h -p xilinx_dsp passes/pmgen/xilinx_dsp.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp48a_pm.h -p xilinx_dsp48a passes/pmgen/xilinx_dsp48a.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_CREG_pm.h -p xilinx_dsp_CREG passes/pmgen/xilinx_dsp_CREG.pmg mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_cascade_pm.h -p xilinx_dsp_cascade passes/pmgen/xilinx_dsp_cascade.pmg mkdir -p passes/pmgen/ gcc -o passes/pmgen/peepopt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/peepopt.cc mkdir -p passes/pmgen/ gcc -o passes/pmgen/xilinx_srl.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_srl.cc mkdir -p passes/proc/ gcc -o passes/proc/proc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_prune.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_prune.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_clean.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_clean.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_rmdead.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rmdead.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_init.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_init.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_arst.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_arst.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_mux.cc mkdir -p passes/proc/ gcc -o passes/proc/proc_dlatch.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dlatch.cc mkdir -p passes/proc/ mkdir -p passes/proc/ gcc -o passes/proc/proc_dff.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dff.cc gcc -o passes/proc/proc_memwr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_memwr.cc mkdir -p passes/sat/ gcc -o passes/sat/sat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sat.cc mkdir -p passes/sat/ gcc -o passes/sat/freduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/freduce.cc mkdir -p passes/sat/ gcc -o passes/sat/eval.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/eval.cc mkdir -p passes/sat/ gcc -o passes/sat/sim.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sim.cc mkdir -p passes/sat/ gcc -o passes/sat/miter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/miter.cc mkdir -p passes/sat/ gcc -o passes/sat/expose.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/expose.cc mkdir -p passes/sat/ gcc -o passes/sat/assertpmux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/assertpmux.cc mkdir -p passes/sat/ gcc -o passes/sat/clk2fflogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/clk2fflogic.cc mkdir -p passes/sat/ gcc -o passes/sat/async2sync.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/async2sync.cc mkdir -p passes/sat/ gcc -o passes/sat/supercover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/supercover.cc mkdir -p passes/sat/ gcc -o passes/sat/fmcombine.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fmcombine.cc mkdir -p passes/sat/ gcc -o passes/sat/mutate.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/mutate.cc mkdir -p passes/sat/ gcc -o passes/sat/cutpoint.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/cutpoint.cc mkdir -p passes/sat/ gcc -o passes/sat/fminit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fminit.cc mkdir -p passes/sat/ mkdir -p passes/techmap/ gcc -o passes/sat/qbfsat.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/qbfsat.cc gcc -o passes/techmap/flatten.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flatten.cc mkdir -p passes/techmap/ gcc -o passes/techmap/techmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/techmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/simplemap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/simplemap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dfflibmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflibmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/maccmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/maccmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/libparse.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/libparse.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' passes/techmap/abc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc9.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' passes/techmap/abc9.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc9_exe.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"berkeley-abc"' passes/techmap/abc9_exe.cc mkdir -p passes/techmap/ gcc -o passes/techmap/abc9_ops.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/abc9_ops.cc mkdir -p passes/techmap/ gcc -o passes/techmap/iopadmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/iopadmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/clkbufmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/clkbufmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/hilomap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/hilomap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_fa.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_fa.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_counter.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_counter.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extract_reduce.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_reduce.cc mkdir -p passes/techmap/ gcc -o passes/techmap/alumacc.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/pmuxtree.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc mkdir -p passes/techmap/ gcc -o passes/techmap/bmuxmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bmuxmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/demuxmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/demuxmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/muxcover.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/muxcover.cc mkdir -p passes/techmap/ gcc -o passes/techmap/aigmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/aigmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/tribuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/tribuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/lut2mux.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/lut2mux.cc mkdir -p passes/techmap/ gcc -o passes/techmap/nlutmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/nlutmap.cc passes/techmap/abc.cc: In member function ‘virtual void {anonymous}::AbcPass::execute(std::vector >, Yosys::RTLIL::Design*)’: passes/techmap/abc.cc:1825:50: warning: ‘g_argidx’ may be used uninitialized in this function [-Wmaybe-uninitialized] 1825 | cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str())); | ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ mkdir -p passes/techmap/ gcc -o passes/techmap/shregmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/shregmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/deminout.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/deminout.cc mkdir -p passes/techmap/ gcc -o passes/techmap/insbuf.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/insbuf.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmvcp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmvcp.cc mkdir -p passes/techmap/ gcc -o passes/techmap/attrmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/zinit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/zinit.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dfflegalize.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflegalize.cc mkdir -p passes/techmap/ gcc -o passes/techmap/dffunmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffunmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/flowmap.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flowmap.cc mkdir -p passes/techmap/ gcc -o passes/techmap/extractinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extractinv.cc mkdir -p passes/tests/ gcc -o passes/tests/test_autotb.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_autotb.cc mkdir -p passes/tests/ gcc -o passes/tests/test_cell.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_cell.cc mkdir -p passes/tests/ gcc -o passes/tests/test_abcloop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_abcloop.cc mkdir -p backends/aiger/ gcc -o backends/aiger/aiger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/aiger.cc mkdir -p backends/aiger/ gcc -o backends/aiger/xaiger.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/xaiger.cc mkdir -p backends/blif/ gcc -o backends/blif/blif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/blif/blif.cc mkdir -p backends/btor/ gcc -o backends/btor/btor.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/btor/btor.cc mkdir -p backends/cxxrtl/ gcc -o backends/cxxrtl/cxxrtl_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/cxxrtl/cxxrtl_backend.cc mkdir -p backends/edif/ gcc -o backends/edif/edif.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/edif/edif.cc mkdir -p backends/firrtl/ gcc -o backends/firrtl/firrtl.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/firrtl/firrtl.cc mkdir -p backends/intersynth/ gcc -o backends/intersynth/intersynth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/intersynth/intersynth.cc mkdir -p backends/json/ gcc -o backends/json/json.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/json/json.cc mkdir -p backends/rtlil/ gcc -o backends/rtlil/rtlil_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/rtlil/rtlil_backend.cc mkdir -p backends/simplec/ gcc -o backends/simplec/simplec.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc mkdir -p backends/smt2/ gcc -o backends/smt2/smt2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc mkdir -p backends/smv/ gcc -o backends/smv/smv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc mkdir -p backends/spice/ gcc -o backends/spice/spice.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/spice/spice.cc mkdir -p backends/table/ gcc -o backends/table/table.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/table/table.cc mkdir -p backends/verilog/ gcc -o backends/verilog/verilog_backend.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/verilog/verilog_backend.cc mkdir -p techlibs/achronix/ gcc -o techlibs/achronix/synth_achronix.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/achronix/synth_achronix.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/synth_anlogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/synth_anlogic.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/anlogic_eqn.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_eqn.cc mkdir -p techlibs/anlogic/ gcc -o techlibs/anlogic/anlogic_fixcarry.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_fixcarry.cc mkdir -p techlibs/common/ gcc -o techlibs/common/synth.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/synth.cc mkdir -p techlibs/common/ gcc -o techlibs/common/prep.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/prep.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/synth_coolrunner2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/synth_coolrunner2.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/coolrunner2_sop.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_sop.cc mkdir -p techlibs/coolrunner2/ gcc -o techlibs/coolrunner2/coolrunner2_fixup.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_fixup.cc mkdir -p techlibs/easic/ gcc -o techlibs/easic/synth_easic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/easic/synth_easic.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/synth_ecp5.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/synth_ecp5.cc mkdir -p techlibs/ecp5/ gcc -o techlibs/ecp5/ecp5_gsr.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/ecp5_gsr.cc mkdir -p techlibs/efinix/ gcc -o techlibs/efinix/synth_efinix.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/synth_efinix.cc mkdir -p techlibs/efinix/ gcc -o techlibs/efinix/efinix_fixcarry.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/efinix_fixcarry.cc mkdir -p techlibs/gatemate/ gcc -o techlibs/gatemate/synth_gatemate.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/synth_gatemate.cc mkdir -p techlibs/gowin/ gcc -o techlibs/gowin/synth_gowin.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/synth_gowin.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/synth_greenpak4.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/synth_greenpak4.cc mkdir -p techlibs/greenpak4/ gcc -o techlibs/greenpak4/greenpak4_dffinv.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/greenpak4_dffinv.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/synth_ice40.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/synth_ice40.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_braminit.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_braminit.cc mkdir -p techlibs/ice40/ gcc -o techlibs/ice40/ice40_opt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_opt.cc mkdir -p techlibs/intel/ gcc -o techlibs/intel/synth_intel.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel/synth_intel.cc mkdir -p techlibs/intel_alm/ gcc -o techlibs/intel_alm/synth_intel_alm.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel_alm/synth_intel_alm.cc mkdir -p techlibs/machxo2/ gcc -o techlibs/machxo2/synth_machxo2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/machxo2/synth_machxo2.cc mkdir -p techlibs/nexus/ gcc -o techlibs/nexus/synth_nexus.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/nexus/synth_nexus.cc mkdir -p techlibs/quicklogic/ mkdir -p techlibs/sf2/ gcc -o techlibs/quicklogic/synth_quicklogic.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/synth_quicklogic.cc gcc -o techlibs/sf2/synth_sf2.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/sf2/synth_sf2.cc mkdir -p techlibs/xilinx/ gcc -o techlibs/xilinx/synth_xilinx.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/synth_xilinx.cc mkdir -p techlibs/xilinx/ gcc -o techlibs/xilinx/xilinx_dffopt.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_dffopt.cc sed -e 's#@CXXFLAGS@#-g -O2 -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I/usr/share/yosys/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \ -e 's#@CXX@#gcc#;' -e 's#@LDFLAGS@#-Wl,-z,relro -Wl,-z,now -Wl,--as-needed -rdynamic#;' -e 's#@LDLIBS@#-lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6#;' \ -e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config chmod +x yosys-config mkdir -p passes/techmap/ gcc -o passes/techmap/filterlib.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/filterlib.cc sed 's|##yosys-sys-path##|sys.path += ["/usr/share/yosys"]|;' < backends/smt2/smtbmc.py > yosys-smtbmc.new chmod +x yosys-smtbmc.new mv yosys-smtbmc.new yosys-smtbmc mkdir -p share/include/kernel/ cp "./"/kernel/yosys.h share/include/kernel/yosys.h mkdir -p share/include/kernel/ cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h mkdir -p share/include/kernel/ cp "./"/kernel/log.h share/include/kernel/log.h mkdir -p share/include/kernel/ cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h mkdir -p share/include/kernel/ cp "./"/kernel/binding.h share/include/kernel/binding.h mkdir -p share/include/kernel/ cp "./"/kernel/register.h share/include/kernel/register.h mkdir -p share/include/kernel/ cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h mkdir -p share/include/kernel/ cp "./"/kernel/celledges.h share/include/kernel/celledges.h mkdir -p share/include/kernel/ cp "./"/kernel/consteval.h share/include/kernel/consteval.h mkdir -p share/include/kernel/ cp "./"/kernel/constids.inc share/include/kernel/constids.inc mkdir -p share/include/kernel/ cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h mkdir -p share/include/kernel/ cp "./"/kernel/modtools.h share/include/kernel/modtools.h mkdir -p share/include/kernel/ cp "./"/kernel/macc.h share/include/kernel/macc.h mkdir -p share/include/kernel/ cp "./"/kernel/utils.h share/include/kernel/utils.h mkdir -p share/include/kernel/ cp "./"/kernel/satgen.h share/include/kernel/satgen.h mkdir -p share/include/kernel/ cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h mkdir -p share/include/kernel/ cp "./"/kernel/ff.h share/include/kernel/ff.h mkdir -p share/include/kernel/ cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h mkdir -p share/include/kernel/ cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h mkdir -p share/include/kernel/ cp "./"/kernel/mem.h share/include/kernel/mem.h mkdir -p share/include/libs/ezsat/ cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h mkdir -p share/include/libs/ezsat/ cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h mkdir -p share/include/libs/fst/ cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h mkdir -p share/include/libs/sha1/ cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h mkdir -p share/include/libs/json11/ cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp mkdir -p share/include/passes/fsm/ cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h mkdir -p share/include/frontends/ast/ cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h mkdir -p share/include/frontends/ast/ cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h mkdir -p share/include/frontends/blif/ cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h mkdir -p share/include/backends/rtlil/ cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc mkdir -p share/include/backends/cxxrtl/ mkdir -p share/include/backends/cxxrtl/ cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h mkdir -p share/include/backends/cxxrtl/ mkdir -p share/python3 cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h cp "./"/backends/smt2/smtio.py share/python3/smtio.py mkdir -p share/achronix/speedster22i/ cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v mkdir -p share/achronix/speedster22i/ cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v mkdir -p share/anlogic mkdir -p share/anlogic cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v mkdir -p share/anlogic mkdir -p share/anlogic mkdir -p share/anlogic cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v mkdir -p share/anlogic cp "./"/techlibs/anlogic/lutram_init_16x4.vh share/anlogic/lutram_init_16x4.vh mkdir -p share/anlogic mkdir -p share/anlogic cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt cp "./"/techlibs/anlogic/brams_map.v share/anlogic/brams_map.v mkdir -p techlibs/anlogic mkdir -p share python3 techlibs/anlogic/brams_init.py cp "./"/techlibs/common/simlib.v share/simlib.v mkdir -p share mkdir -p share cp "./"/techlibs/common/simcells.v share/simcells.v cp "./"/techlibs/common/techmap.v share/techmap.v mkdir -p share cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v mkdir -p share cp "./"/techlibs/common/adff2dff.v share/adff2dff.v mkdir -p share cp "./"/techlibs/common/dff2ff.v share/dff2ff.v mkdir -p share mkdir -p share cp "./"/techlibs/common/gate2lut.v share/gate2lut.v cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v mkdir -p share cp "./"/techlibs/common/cells.lib share/cells.lib mkdir -p share cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v mkdir -p share mkdir -p share cp "./"/techlibs/common/abc9_model.v share/abc9_model.v touch techlibs/anlogic/brams_init.mk cp "./"/techlibs/common/abc9_map.v share/abc9_map.v mkdir -p share mkdir -p share cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v mkdir -p share/coolrunner2 mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v mkdir -p share/coolrunner2 mkdir -p share/coolrunner2 cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v mkdir -p share/coolrunner2 mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt mkdir -p share/ecp5 cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v mkdir -p share/ecp5 cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt mkdir -p share/ecp5 mkdir -p share/ecp5 cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v mkdir -p share/ecp5 mkdir -p techlibs/ecp5 cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v python3 techlibs/ecp5/brams_init.py mkdir -p techlibs/ecp5 python3 techlibs/ecp5/brams_connect.py mkdir -p share/efinix mkdir -p share/efinix touch techlibs/ecp5/brams_init.mk cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v mkdir -p share/efinix mkdir -p share/efinix cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v mkdir -p share/efinix cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt mkdir -p share/gatemate mkdir -p share/gatemate cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v mkdir -p share/gatemate mkdir -p share/gatemate mkdir -p share/gatemate cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v touch techlibs/ecp5/brams_connect.mk cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh mkdir -p share/gatemate cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh mkdir -p share/gowin cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v mkdir -p share/gowin cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v mkdir -p share/gowin cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt mkdir -p share/gowin mkdir -p share/gowin cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt mkdir -p share/gowin mkdir -p techlibs/gowin mkdir -p share/greenpak4 python3 techlibs/gowin/brams_init.py mkdir -p share/greenpak4 cp "./"/techlibs/gowin/brams_init3.vh share/gowin/brams_init3.vh cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v touch techlibs/gowin/brams_init.mk mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v mkdir -p share/greenpak4 cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib mkdir -p share/ice40 cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v mkdir -p share/ice40 cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v mkdir -p share/ice40 cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v mkdir -p share/ice40 mkdir -p share/ice40 cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v mkdir -p techlibs/ice40 python3 techlibs/ice40/brams_init.py mkdir -p share/intel/common mkdir -p share/intel/common cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt mkdir -p share/intel/common cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v mkdir -p share/intel/common mkdir -p share/intel/max10 cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v mkdir -p share/intel/cyclone10lp touch techlibs/ice40/brams_init.mk cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v mkdir -p share/intel/cycloneiv mkdir -p share/intel/cycloneive mkdir -p share/intel/max10 cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v mkdir -p share/intel/cyclone10lp cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v mkdir -p share/intel/cycloneiv mkdir -p share/intel/cycloneive cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/cyclonev cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v mkdir -p share/intel_alm/common mkdir -p share/intel_alm/common cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v mkdir -p share/intel_alm/common mkdir -p share/machxo2 cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v cp "./"/techlibs/machxo2/cells_map.v share/machxo2/cells_map.v mkdir -p share/machxo2 mkdir -p share/nexus cp "./"/techlibs/machxo2/cells_sim.v share/machxo2/cells_sim.v cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt cp "./"/techlibs/nexus/brams_init.vh share/nexus/brams_init.vh mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v mkdir -p share/nexus cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt cp "./"/techlibs/nexus/lrams_init.vh share/nexus/lrams_init.vh mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt mkdir -p share/nexus mkdir -p share/nexus cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v mkdir -p share/nexus mkdir -p share/quicklogic cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v mkdir -p share/quicklogic mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v mkdir -p share/quicklogic mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v mkdir -p share/quicklogic mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v mkdir -p share/quicklogic cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v mkdir -p share/sf2 mkdir -p share/sf2 cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v mkdir -p share/sf2 mkdir -p share/xilinx cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc2v_brams.txt share/xilinx/xc2v_brams.txt cp "./"/techlibs/xilinx/xc2v_brams_map.v share/xilinx/xc2v_brams_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc3sa_brams.txt share/xilinx/xc3sa_brams.txt cp "./"/techlibs/xilinx/xc3sda_brams.txt share/xilinx/xc3sda_brams.txt mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc6s_brams.txt share/xilinx/xc6s_brams.txt cp "./"/techlibs/xilinx/xc6s_brams_map.v share/xilinx/xc6s_brams_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc7_xcu_brams.txt share/xilinx/xc7_xcu_brams.txt mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc7_brams_map.v share/xilinx/xc7_brams_map.v cp "./"/techlibs/xilinx/xcu_brams_map.v share/xilinx/xcu_brams_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xcup_urams.txt share/xilinx/xcup_urams.txt cp "./"/techlibs/xilinx/xcup_urams_map.v share/xilinx/xcup_urams_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/lut4_lutrams.txt share/xilinx/lut4_lutrams.txt cp "./"/techlibs/xilinx/lut6_lutrams.txt share/xilinx/lut6_lutrams.txt mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/lutrams_map.v share/xilinx/lutrams_map.v cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v mkdir -p share/xilinx mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v mkdir -p share/xilinx cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v mkdir -p share/xilinx mkdir -p techlibs/xilinx cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v python3 techlibs/xilinx/brams_init.py mkdir -p kernel/ gcc -o kernel/version_2156e20.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_2156e20.cc mkdir -p kernel/ gcc -o kernel/register.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc mkdir -p frontends/rtlil/ gcc -o frontends/rtlil/rtlil_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_parser.tab.cc mkdir -p frontends/rtlil/ gcc -o frontends/rtlil/rtlil_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_lexer.cc mkdir -p frontends/verilog/ touch techlibs/xilinx/brams_init.mk gcc -o frontends/verilog/verilog_parser.tab.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc mkdir -p frontends/verilog/ flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l mkdir -p passes/pmgen/ mkdir -p passes/pmgen/ gcc -o passes/pmgen/test_pmgen.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/test_pmgen.cc gcc -o passes/pmgen/ice40_wrapcarry.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_wrapcarry.cc mkdir -p passes/pmgen/ gcc -o passes/pmgen/xilinx_dsp.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_dsp.cc mkdir -p ./ mkdir -p share/anlogic cp techlibs/anlogic/brams_init_16.vh share/anlogic/brams_init_16.vh gcc -o yosys-filterlib -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -rdynamic passes/techmap/filterlib.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 mkdir -p share/anlogic cp techlibs/anlogic/brams_init_9.vh share/anlogic/brams_init_9.vh mkdir -p share/anlogic mkdir -p share/ecp5 cp techlibs/anlogic/brams_init_8.vh share/anlogic/brams_init_8.vh cp techlibs/ecp5/bram_init_1_2_4.vh share/ecp5/bram_init_1_2_4.vh mkdir -p share/ecp5 cp techlibs/ecp5/bram_init_9_18_36.vh share/ecp5/bram_init_9_18_36.vh mkdir -p share/ecp5 mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_1.vh share/ecp5/bram_conn_1.vh cp techlibs/ecp5/bram_conn_2.vh share/ecp5/bram_conn_2.vh mkdir -p share/ecp5 mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_9.vh share/ecp5/bram_conn_9.vh cp techlibs/ecp5/bram_conn_4.vh share/ecp5/bram_conn_4.vh mkdir -p share/ecp5 mkdir -p share/ecp5 cp techlibs/ecp5/bram_conn_18.vh share/ecp5/bram_conn_18.vh cp techlibs/ecp5/bram_conn_36.vh share/ecp5/bram_conn_36.vh mkdir -p share/gowin cp techlibs/gowin/bram_init_16.vh share/gowin/bram_init_16.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init1.vh share/ice40/brams_init1.vh mkdir -p share/ice40 cp techlibs/ice40/brams_init2.vh share/ice40/brams_init2.vh mkdir -p share/ice40 mkdir -p share/xilinx cp techlibs/ice40/brams_init3.vh share/ice40/brams_init3.vh cp techlibs/xilinx/brams_init_36.vh share/xilinx/brams_init_36.vh mkdir -p share/xilinx mkdir -p share/xilinx cp techlibs/xilinx/brams_init_18.vh share/xilinx/brams_init_18.vh cp techlibs/xilinx/brams_init_32.vh share/xilinx/brams_init_32.vh mkdir -p share/xilinx cp techlibs/xilinx/brams_init_16.vh share/xilinx/brams_init_16.vh mkdir -p share/xilinx mkdir -p share/xilinx cp techlibs/xilinx/brams_init_8.vh share/xilinx/brams_init_8.vh cp techlibs/xilinx/brams_init_9.vh share/xilinx/brams_init_9.vh mkdir -p frontends/verilog/ gcc -o frontends/verilog/verilog_lexer.o -c -Wdate-time -D_FORTIFY_SOURCE=2 -g -O2 -ffile-prefix-map=/build/yosys-cNltON/yosys-0.15=. -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc gcc -o yosys -Wl,-z,relro -Wl,-z,now -Wl,--as-needed -rdynamic kernel/version_2156e20.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/subcircuit/subcircuit.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o frontends/aiger/aigerparse.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/stat.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/qwp.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/qbfsat.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/intersynth/intersynth.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/gatemate/synth_gatemate.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/machxo2/synth_machxo2.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o -lstdc++ -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 cd manual && 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LaTeX Warning: Label(s) may have changed. Rerun to get cross-references right. ) (see the transcript file for additional information){/usr/share/texlive/texmf-d ist/fonts/enc/dvips/inconsolata/i4-t1-0.enc}{/usr/share/texlive/texmf-dist/font s/enc/dvips/base/8r.enc} Output written on APPNOTE_010_Verilog_to_BLIF.pdf (3 pages, 121700 bytes). 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Transcript written on APPNOTE_010_Verilog_to_BLIF.log. ++ md5sum + new_md5='4a60d467c86bf7bda036c4126ef7f702 -' + '[' '4a60d467c86bf7bda036c4126ef7f702 -' '!=' '4a60d467c86bf7bda036c4126ef7f702 -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_010_Verilog_to_BLIF.pdf + mv -f APPNOTE_010_Verilog_to_BLIF.pdf.without_pdf_id APPNOTE_010_Verilog_to_BLIF.pdf + touch APPNOTE_010_Verilog_to_BLIF.ok + for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation APPNOTE_012_Verilog_to_BTOR + '[' -f APPNOTE_011_Design_Investigation.ok -a APPNOTE_011_Design_Investigation.ok -nt APPNOTE_011_Design_Investigation.tex ']' + '[' -f APPNOTE_011_Design_Investigation/make.sh ']' + cd APPNOTE_011_Design_Investigation + bash make.sh + false + for dot_file in *.dot + pdf_file=cmos_00.pdf + dot -Tpdf -o cmos_00.pdf cmos_00.dot + for dot_file in *.dot + pdf_file=cmos_01.pdf + dot -Tpdf -o cmos_01.pdf cmos_01.dot + for dot_file in *.dot + pdf_file=example_00.pdf + dot -Tpdf -o example_00.pdf example_00.dot + for dot_file in *.dot + pdf_file=example_01.pdf + dot -Tpdf -o example_01.pdf example_01.dot + for dot_file in *.dot + pdf_file=example_02.pdf + dot -Tpdf -o example_02.pdf example_02.dot + for dot_file in *.dot + pdf_file=example_03.pdf + dot -Tpdf -o example_03.pdf example_03.dot + for dot_file in *.dot + pdf_file=memdemo_00.pdf + dot -Tpdf -o memdemo_00.pdf memdemo_00.dot + for dot_file in *.dot + pdf_file=memdemo_01.pdf + dot -Tpdf -o memdemo_01.pdf memdemo_01.dot + for dot_file in *.dot + pdf_file=splice.pdf + dot -Tpdf -o splice.pdf splice.dot + for dot_file in *.dot + pdf_file=submod_00.pdf + dot -Tpdf -o submod_00.pdf submod_00.dot + for dot_file in *.dot + pdf_file=submod_01.pdf + dot -Tpdf -o submod_01.pdf submod_01.dot + for dot_file in *.dot + pdf_file=submod_02.pdf + dot -Tpdf -o submod_02.pdf submod_02.dot + for dot_file in *.dot + pdf_file=submod_03.pdf + dot -Tpdf -o submod_03.pdf submod_03.dot + for dot_file in *.dot + pdf_file=sumprod_00.pdf + dot -Tpdf -o sumprod_00.pdf sumprod_00.dot + for dot_file in *.dot + pdf_file=sumprod_01.pdf + dot -Tpdf -o sumprod_01.pdf sumprod_01.dot + for dot_file in *.dot + pdf_file=sumprod_02.pdf + dot -Tpdf -o sumprod_02.pdf sumprod_02.dot + for dot_file in *.dot + pdf_file=sumprod_03.pdf + dot -Tpdf -o sumprod_03.pdf sumprod_03.dot + for dot_file in *.dot + pdf_file=sumprod_04.pdf + dot -Tpdf -o sumprod_04.pdf sumprod_04.dot + for dot_file in *.dot + pdf_file=sumprod_05.pdf + dot -Tpdf -o sumprod_05.pdf sumprod_05.dot + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20220326155523Z)#' cmos_00.pdf cmos_01.pdf example_00.pdf example_01.pdf example_02.pdf example_03.pdf memdemo_00.pdf memdemo_01.pdf splice.pdf submod_00.pdf submod_01.pdf submod_02.pdf submod_03.pdf sumprod_00.pdf sumprod_01.pdf sumprod_02.pdf sumprod_03.pdf sumprod_04.pdf sumprod_05.pdf + cd .. ++ '[' -f APPNOTE_011_Design_Investigation.aux ']' ++ true + old_md5= + pdflatex -shell-escape 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LaTeX Warning: Label(s) may have changed. Rerun to get cross-references right. ) (see the transcript file for additional information){/usr/share/texlive/texmf-d ist/fonts/enc/dvips/base/8r.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/ inconsolata/i4-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsola ta/i4-t1-0.enc} Output written on APPNOTE_012_Verilog_to_BTOR.pdf (3 pages, 132449 bytes). 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Transcript written on APPNOTE_012_Verilog_to_BTOR.log. ++ md5sum + new_md5='fc9dceaa63440fd2a3c080744393ba5d -' + '[' 'fc9dceaa63440fd2a3c080744393ba5d -' '!=' 'fc9dceaa63440fd2a3c080744393ba5d -' ']' + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' APPNOTE_012_Verilog_to_BTOR.pdf + mv -f APPNOTE_012_Verilog_to_BTOR.pdf.without_pdf_id APPNOTE_012_Verilog_to_BTOR.pdf + touch APPNOTE_012_Verilog_to_BTOR.ok cd manual && PDF_DATE=D:20220326155523Z bash presentation.sh + false + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux '*.snm' '*.nav' '*.toc' md5sum: '*.snm': No such file or directory md5sum: '*.nav': No such file or directory md5sum: '*.toc': No such file or directory + make -C PRESENTATION_Intro make[3]: Entering directory '/build/yosys-cNltON/yosys-0.15/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys counter.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `counter.ys' -- 1. Executing Verilog-2005 frontend: counter.v Parsing Verilog input from `counter.v' to AST representation. Generating RTLIL representation for module `\counter'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \counter 2.2. Analyzing design hierarchy.. Top module: \counter Removed 0 unused modules. 3. Generating Graphviz representation of design. Writing dot description to `counter_00.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_00.dot' > 'counter_00.pdf.new' && mv 'counter_00.pdf.new' 'counter_00.pdf' 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter. Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). 4.5. Executing PROC_ARST pass (detect async resets in processes). 4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\counter.$proc$counter.v:6$1'. 1/1: $0\count[1:0] 4.7. Executing PROC_DLATCH pass (convert process syncs to latches). 4.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'. created $dff cell `$procdff$8' with positive edge clock. 4.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'. Removing empty process `counter.$proc$counter.v:6$1'. Cleaned up 2 empty switches. 4.11. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00). Adding EN signal on $auto$ff.cc:262:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 2 unused cells and 5 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 5.16. Finished OPT passes. (There is nothing left to do.) 6. Executing MEMORY pass. 6.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 6.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 6.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 6.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 6.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 6.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 6.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 6.9. Executing MEMORY_COLLECT pass (generating $mem cells). 6.10. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 7. Executing OPT pass (performing simple optimizations). 7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 7.6. Executing OPT_DFF pass (perform DFF optimizations). 7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 7.9. Finished OPT passes. (There is nothing left to do.) 8. Executing FSM pass (extract and optimize FSM). 8.1. Executing FSM_DETECT pass (finding FSMs in design). 8.2. Executing FSM_EXTRACT pass (extracting FSM from design). 8.3. Executing FSM_OPT pass (simple optimizations of FSMs). 8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 8.5. Executing FSM_OPT pass (simple optimizations of FSMs). 8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 9. Executing OPT pass (performing simple optimizations). 9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 9.6. Executing OPT_DFF pass (perform DFF optimizations). 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 9.9. Finished OPT passes. (There is nothing left to do.) 10. Generating Graphviz representation of design. Writing dot description to `counter_01.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_01.dot' > 'counter_01.pdf.new' && mv 'counter_01.pdf.new' 'counter_01.pdf' 11. Executing TECHMAP pass (map to technology primitives). 11.1. Executing Verilog-2005 frontend: /build/yosys-cNltON/yosys-0.15/share/techmap.v Parsing Verilog input from `/build/yosys-cNltON/yosys-0.15/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 11.2. Continuing TECHMAP pass. Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $and. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. No more expansions possible. 12. Executing OPT pass (performing simple optimizations). 12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.6. Executing OPT_DFF pass (perform DFF optimizations). 12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. Removed 1 unused cells and 32 unused wires. 12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.9. Rerunning OPT passes. (Maybe there is more to do..) 12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \counter.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \counter. Performed a total of 0 changes. 12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\counter'. Removed a total of 0 cells. 12.13. Executing OPT_DFF pass (perform DFF optimizations). 12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \counter.. 12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module counter. 12.16. Finished OPT passes. (There is nothing left to do.) 13. Executing SPLITNETS pass (splitting up multi-bit signals). Removed 0 unused cells and 2 unused wires. 14. Generating Graphviz representation of design. Writing dot description to `counter_02.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_02.dot' > 'counter_02.pdf.new' && mv 'counter_02.pdf.new' 'counter_02.pdf' 15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_. final dff cell mappings: unmapped dff cell: $_DFF_N_ \DFF _DFF_P_ (.C( C), .D( D), .Q( Q)); unmapped dff cell: $_DFF_NN0_ unmapped dff cell: $_DFF_NN1_ unmapped dff cell: $_DFF_NP0_ unmapped dff cell: $_DFF_NP1_ unmapped dff cell: $_DFF_PN0_ unmapped dff cell: $_DFF_PN1_ unmapped dff cell: $_DFF_PP0_ unmapped dff cell: $_DFF_PP1_ unmapped dff cell: $_DFFSR_NNN_ unmapped dff cell: $_DFFSR_NNP_ unmapped dff cell: $_DFFSR_NPN_ unmapped dff cell: $_DFFSR_NPP_ unmapped dff cell: $_DFFSR_PNN_ unmapped dff cell: $_DFFSR_PNP_ unmapped dff cell: $_DFFSR_PPN_ unmapped dff cell: $_DFFSR_PPP_ 15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). Mapping DFF cells in module `\counter': mapped 2 $_DFF_P_ cells to \DFF cells. 16. Executing ABC pass (technology mapping using ABC). 16.1. Extracting gate netlist of module `\counter' to `/input.blif'.. Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs. 16.1.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_Intro/mycells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Library "demo" from "/manual/PRESENTATION_Intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 16.1.2. Re-integrating ABC results. ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 4 ABC RESULTS: NOT cells: 3 ABC RESULTS: internal signals: 5 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 2 Removing temp directory. Removed 0 unused cells and 10 unused wires. 17. Generating Graphviz representation of design. 17.1. Executing Verilog-2005 frontend: mycells.v Parsing Verilog input from `mycells.v' to AST representation. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Successfully finished Verilog frontend. 17.2. Continuing show pass. Writing dot description to `counter_03.dot'. Dumping module counter to page 1. Exec: dot -Tpdf 'counter_03.dot' > 'counter_03.pdf.new' && mv 'counter_03.pdf.new' 'counter_03.pdf' End of script. Logfile hash: 56e33edd93, CPU: user 0.08s system 0.01s, MEM: 14.04 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 43% 4x show (0 sec), 28% 1x abc (0 sec), ... make[3]: Leaving directory '/build/yosys-cNltON/yosys-0.15/manual/PRESENTATION_Intro' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20220326155523Z)#' PRESENTATION_Intro/counter_00.pdf PRESENTATION_Intro/counter_01.pdf PRESENTATION_Intro/counter_02.pdf PRESENTATION_Intro/counter_03.pdf + make -C PRESENTATION_ExSyn make[3]: Entering directory '/build/yosys-cNltON/yosys-0.15/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format pdf' -- -- Executing script file `proc_01.ys' -- 1. Executing Verilog-2005 frontend: proc_01.v Parsing Verilog input from `proc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$proc_01.v:2$1 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 0 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_01.v:2$1'. 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_01.v:2$1'. 1/1: $0\Q[0:0] 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'. created $adff cell `$procdff$2' with positive edge clock and positive level reset. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_01.v:2$1'. Cleaned up 0 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_01.dot' > 'proc_01.pdf.new' && mv 'proc_01.pdf.new' 'proc_01.pdf' End of script. Logfile hash: 046f8ddc59, CPU: user 0.01s system 0.00s, MEM: 11.55 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 92% 1x show (0 sec), 2% 1x clean (0 sec), ... ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format pdf' -- -- Executing script file `proc_02.ys' -- 1. Executing Verilog-2005 frontend: proc_02.v Parsing Verilog input from `proc_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$proc_02.v:3$1 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 0 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \R in `\test.$proc$proc_02.v:3$1'. 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_02.v:3$1'. 1/1: $0\Q[0:0] 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'. Warning: Async reset value `\RV' is not constant! created $aldff cell `$procdff$2' with positive edge clock and positive level non-const reset. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$proc_02.v:3$1'. Cleaned up 0 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 0 unused cells and 1 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_02.dot' > 'proc_02.pdf.new' && mv 'proc_02.pdf.new' 'proc_02.pdf' Warnings: 1 unique messages, 1 total End of script. Logfile hash: aa9cd0ea49, CPU: user 0.01s system 0.00s, MEM: 11.74 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 89% 1x show (0 sec), 3% 1x clean (0 sec), ... ../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format pdf' -- -- Executing script file `proc_03.ys' -- 1. Executing Verilog-2005 frontend: proc_03.v Parsing Verilog input from `proc_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$proc_03.v:3$1'. 1/1: $0\Y[0:0] 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'. 3.8. Executing PROC_DFF pass (convert process syncs to FFs). 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'. Removing empty process `test.$proc$proc_03.v:3$1'. Cleaned up 2 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 0 unused cells and 4 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `proc_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'proc_03.dot' > 'proc_03.pdf.new' && mv 'proc_03.pdf.new' 'proc_03.pdf' End of script. Logfile hash: 80ebe801ef, CPU: user 0.01s system 0.00s, MEM: 11.81 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 86% 1x show (0 sec), 4% 1x clean (0 sec), ... ../../yosys -p 'script opt_01.ys; show -notitle -prefix opt_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script opt_01.ys; show -notitle -prefix opt_01 -format pdf' -- -- Executing script file `opt_01.ys' -- 1. Executing Verilog-2005 frontend: opt_01.v Parsing Verilog input from `opt_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $ternary$opt_01.v:2$1. Removed 1 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Optimizing cells in module \test. Performed a total of 1 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_01.dot' > 'opt_01.pdf.new' && mv 'opt_01.pdf.new' 'opt_01.pdf' End of script. Logfile hash: 9f52b2c276, CPU: user 0.01s system 0.00s, MEM: 11.69 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 72% 1x show (0 sec), 9% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_02.ys; show -notitle -prefix opt_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script opt_02.ys; show -notitle -prefix opt_02 -format pdf' -- -- Executing script file `opt_02.ys' -- 1. Executing Verilog-2005 frontend: opt_02.v Parsing Verilog input from `opt_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_02.dot' > 'opt_02.pdf.new' && mv 'opt_02.pdf.new' 'opt_02.pdf' End of script. Logfile hash: 5a4000bb43, CPU: user 0.01s system 0.00s, MEM: 11.65 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 77% 1x show (0 sec), 8% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_03.ys; show -notitle -prefix opt_03 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script opt_03.ys; show -notitle -prefix opt_03 -format pdf' -- -- Executing script file `opt_03.ys' -- 1. Executing Verilog-2005 frontend: opt_03.v Parsing Verilog input from `opt_03.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 1 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.6. Executing OPT_DFF pass (perform DFF optimizations). 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.9. Rerunning OPT passes. (Maybe there is more to do..) 3.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 3.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 3.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 3.13. Executing OPT_DFF pass (perform DFF optimizations). 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 3.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 3.16. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `opt_03.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_03.dot' > 'opt_03.pdf.new' && mv 'opt_03.pdf.new' 'opt_03.pdf' End of script. Logfile hash: 0cd024bc02, CPU: user 0.01s system 0.01s, MEM: 11.59 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 73% 1x show (0 sec), 8% 3x opt_expr (0 sec), ... ../../yosys -p 'script opt_04.ys; show -notitle -prefix opt_04 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script opt_04.ys; show -notitle -prefix opt_04 -format pdf' -- -- Executing script file `opt_04.ys' -- 1. Executing Verilog-2005 frontend: opt_04.v Parsing Verilog input from `opt_04.v' to AST representation. Generating RTLIL representation for module `\test'. Warning: wire '\Q1' is assigned in a block at opt_04.v:8.3-8.11. Warning: wire '\Q2' is assigned in a block at opt_04.v:12.3-12.11. Warning: wire '\Q2' is assigned in a block at opt_04.v:14.3-14.11. Warning: wire '\Q3' is assigned in a block at opt_04.v:17.2-17.10. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$opt_04.v:10$2 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \ARST in `\test.$proc$opt_04.v:10$2'. Found async reset \ARST in `\test.$proc$opt_04.v:6$1'. 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$opt_04.v:16$3'. Creating decoders for process `\test.$proc$opt_04.v:10$2'. 1/1: $0\Q2[7:0] Creating decoders for process `\test.$proc$opt_04.v:6$1'. 1/1: $0\Q1[7:0] 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\Q3' using process `\test.$proc$opt_04.v:16$3'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\Q2' using process `\test.$proc$opt_04.v:10$2'. created $adff cell `$procdff$5' with positive edge clock and positive level reset. Creating register for signal `\test.\Q1' using process `\test.$proc$opt_04.v:6$1'. created $adff cell `$procdff$6' with positive edge clock and positive level reset. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$opt_04.v:16$3'. Removing empty process `test.$proc$opt_04.v:10$2'. Removing empty process `test.$proc$opt_04.v:6$1'. Cleaned up 0 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_DFF pass (perform DFF optimizations). Handling const CLK on $procdff$5 ($adff) from module test (removing D path). Handling D = Q on $procdff$6 ($adff) from module test (removing D path). Setting constant 0-bit at position 0 on $procdff$6 ($dlatch) from module test. Setting constant 1-bit at position 1 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 2 on $procdff$6 ($dlatch) from module test. Setting constant 1-bit at position 3 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 4 on $procdff$6 ($dlatch) from module test. Setting constant 1-bit at position 5 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 6 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 7 on $procdff$6 ($dlatch) from module test. Setting constant 0-bit at position 0 on $procdff$5 ($dlatch) from module test. Setting constant 1-bit at position 1 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 2 on $procdff$5 ($dlatch) from module test. Setting constant 1-bit at position 3 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 4 on $procdff$5 ($dlatch) from module test. Setting constant 1-bit at position 5 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 6 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 7 on $procdff$5 ($dlatch) from module test. Setting constant 0-bit at position 0 on $procdff$4 ($dff) from module test. Setting constant 1-bit at position 1 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 2 on $procdff$4 ($dff) from module test. Setting constant 1-bit at position 3 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 4 on $procdff$4 ($dff) from module test. Setting constant 1-bit at position 5 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 6 on $procdff$4 ($dff) from module test. Setting constant 0-bit at position 7 on $procdff$4 ($dff) from module test. 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 3 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `opt_04.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'opt_04.dot' > 'opt_04.pdf.new' && mv 'opt_04.pdf.new' 'opt_04.pdf' Warnings: 4 unique messages, 4 total End of script. Logfile hash: 7981d14fdf, CPU: user 0.01s system 0.00s, MEM: 11.88 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 78% 1x show (0 sec), 7% 4x opt_expr (0 sec), ... ../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format pdf' -- -- Executing script file `memory_01.ys' -- 1. Executing Verilog-2005 frontend: memory_01.v Parsing Verilog input from `memory_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 4 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_01.v:5$2'. 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$7' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$9' with positive edge clock. Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'. created $dff cell `$procdff$10' with positive edge clock. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_01.v:5$2'. Cleaned up 0 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 3 unused cells and 7 unused wires. 4. Executing MEMORY pass. 4.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing test.mem write port 0. 4.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\mem'[0] in module `\test': merging output FF to cell. Write port 0: non-transparent. 4.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 9 unused wires. 4.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.9. Executing MEMORY_COLLECT pass (generating $mem cells). 4.10. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory \mem in module \test: created 2 $dff cells and 0 static cells of width 8. Extracted data FF from read port 0 of test.mem: $\mem$rdreg[0] read interface: 1 $dff and 1 $mux cells. write interface: 2 write mux blocks. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 6 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $memory\mem[1]$23 ($dff) from module test (D = \DIN, Q = \mem[1]). Adding EN signal on $memory\mem[0]$21 ($dff) from module test (D = \DIN, Q = \mem[0]). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 2 unused cells and 2 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Rerunning OPT passes. (Maybe there is more to do..) 5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.20. Executing OPT_DFF pass (perform DFF optimizations). 5.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.22. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.23. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_01.dot' > 'memory_01.pdf.new' && mv 'memory_01.pdf.new' 'memory_01.pdf' End of script. Logfile hash: 9a22118a5b, CPU: user 0.04s system 0.00s, MEM: 11.92 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 58% 1x show (0 sec), 11% 5x opt_expr (0 sec), ... ../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format pdf' -- -- Executing script file `memory_02.ys' -- 1. Executing Verilog-2005 frontend: memory_02.v Parsing Verilog input from `memory_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$memory_02.v:17$10 in module test. Marked 1 switch rules as full_case in process $proc$memory_02.v:13$3 in module test. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 8 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$memory_02.v:24$19'. Creating decoders for process `\test.$proc$memory_02.v:21$17'. Creating decoders for process `\test.$proc$memory_02.v:17$10'. 1/3: $1$memwr$\memory$memory_02.v:19$2_EN[7:0]$16 2/3: $1$memwr$\memory$memory_02.v:19$2_DATA[7:0]$15 3/3: $1$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$14 Creating decoders for process `\test.$proc$memory_02.v:13$3'. 1/3: $1$memwr$\memory$memory_02.v:15$1_EN[7:0]$9 2/3: $1$memwr$\memory$memory_02.v:15$1_DATA[7:0]$8 3/3: $1$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$7 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$19'. created $dff cell `$procdff$39' with positive edge clock. Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$17'. created $dff cell `$procdff$40' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$10'. created $dff cell `$procdff$41' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$10'. created $dff cell `$procdff$42' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$10'. created $dff cell `$procdff$43' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$44' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$45' with positive edge clock. Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'. created $dff cell `$procdff$46' with positive edge clock. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$memory_02.v:24$19'. Removing empty process `test.$proc$memory_02.v:21$17'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$10'. Removing empty process `test.$proc$memory_02.v:17$10'. Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'. Removing empty process `test.$proc$memory_02.v:13$3'. Cleaned up 2 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. Removed 6 unused cells and 26 unused wires. 4. Executing MEMORY pass. 4.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing test.memory write port 0. Analyzing test.memory write port 1. 4.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\memory'[0] in module `\test': merging output FF to cell. Checking read port `\memory'[1] in module `\test': merging output FF to cell. 4.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 2 unused cells and 18 unused wires. 4.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory test.memory by address: Consolidating write ports of memory test.memory by address: Consolidating write ports of memory test.memory using sat-based resource sharing: 4.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.9. Executing MEMORY_COLLECT pass (generating $mem cells). 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Consolidated identical input bits for $mux cell $procmux$31: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] } Consolidated identical input bits for $mux cell $procmux$22: Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] } Optimizing cells in module \test. Performed a total of 2 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 4 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 2 unused wires. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Rerunning OPT passes. (Maybe there is more to do..) 5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.20. Executing OPT_DFF pass (perform DFF optimizations). 5.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.22. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.23. Finished OPT passes. (There is nothing left to do.) 6. Generating Graphviz representation of design. Writing dot description to `memory_02.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'memory_02.dot' > 'memory_02.pdf.new' && mv 'memory_02.pdf.new' 'memory_02.pdf' End of script. Logfile hash: 4f259ae542, CPU: user 0.03s system 0.00s, MEM: 11.88 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 67% 1x show (0 sec), 7% 5x opt_clean (0 sec), ... ../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format pdf' -- -- Executing script file `techmap_01.ys' -- 1. Executing Verilog-2005 frontend: techmap_01.v Parsing Verilog input from `techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: techmap_01_map.v Parsing Verilog input from `techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `techmap_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'techmap_01.dot' > 'techmap_01.pdf.new' && mv 'techmap_01.pdf.new' 'techmap_01.pdf' End of script. Logfile hash: b9ee13b07b, CPU: user 0.01s system 0.00s, MEM: 11.47 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 91% 1x show (0 sec), 3% 1x techmap (0 sec), ... ../../yosys -p 'script abc_01.ys; show -notitle -prefix abc_01 -format pdf' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Running command `script abc_01.ys; show -notitle -prefix abc_01 -format pdf' -- -- Executing script file `abc_01.ys' -- 1. Executing Verilog-2005 frontend: abc_01.v Parsing Verilog input from `abc_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: abc_01_cells.v Parsing Verilog input from `abc_01_cells.v' to AST representation. Generating RTLIL representation for module `\BUF'. Generating RTLIL representation for module `\NOT'. Generating RTLIL representation for module `\NAND'. Generating RTLIL representation for module `\NOR'. Generating RTLIL representation for module `\DFF'. Generating RTLIL representation for module `\DFFSR'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \test 3.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 3 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). 4.5. Executing PROC_ARST pass (detect async resets in processes). 4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$abc_01.v:5$1'. 4.7. Executing PROC_DLATCH pass (convert process syncs to latches). 4.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\y' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$3' with positive edge clock. Creating register for signal `\test.\q1' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$4' with positive edge clock. Creating register for signal `\test.\q2' using process `\test.$proc$abc_01.v:5$1'. created $dff cell `$procdff$5' with positive edge clock. 4.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$abc_01.v:5$1'. Cleaned up 0 empty switches. 4.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.6. Executing OPT_DFF pass (perform DFF optimizations). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 0 unused cells and 3 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.9. Rerunning OPT passes. (Maybe there is more to do..) 5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 5.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 5.13. Executing OPT_DFF pass (perform DFF optimizations). 5.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 5.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 5.16. Finished OPT passes. (There is nothing left to do.) 6. Executing TECHMAP pass (map to technology primitives). 6.1. Executing Verilog-2005 frontend: /build/yosys-cNltON/yosys-0.15/share/techmap.v Parsing Verilog input from `/build/yosys-cNltON/yosys-0.15/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 6.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $reduce_xor. Using extmapper simplemap for cells of type $dff. No more expansions possible. 7. Executing ABC pass (technology mapping using ABC). 7.1. Summary of detected clock domains: 9 cells in clk=\clk, en={ } 7.2. Extracting gate netlist of module `\test' to `/input.blif'.. Found matching posedge clock domain: \clk Extracted 9 gates and 12 wires to a netlist network with 3 inputs and 1 outputs. 7.2.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /manual/PRESENTATION_ExSyn/abc_01_cells.lib ABC: Parsing finished successfully. Parsing time = 0.00 sec ABC: Warning: Templates are not defined. ABC: Libery parser cannot read "time_unit". Assuming time_unit : "1ns". ABC: Libery parser cannot read "capacitive_load_unit". Assuming capacitive_load_unit(1, pf). ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR". ABC: Library "demo" from "/manual/PRESENTATION_ExSyn/abc_01_cells.lib" has 4 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 0 dont_use). Time = 0.00 sec ABC: Memory = 0.00 MB. Time = 0.00 sec ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: 7 registers in this network have don't-care init values. ABC: The don't-care are assumed to be 0. The result may not verify. ABC: Use command "print_latch" to see the init values of registers. ABC: Use command "zero" to convert or "init" to change the values. ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif /output.blif 7.2.2. Re-integrating ABC results. ABC RESULTS: BUF cells: 3 ABC RESULTS: NAND cells: 2 ABC RESULTS: NOR cells: 5 ABC RESULTS: NOT cells: 3 ABC RESULTS: _dff_ cells: 3 ABC RESULTS: internal signals: 8 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 1 Removing temp directory. Removed 0 unused cells and 9 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `abc_01.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'abc_01.dot' > 'abc_01.pdf.new' && mv 'abc_01.pdf.new' 'abc_01.pdf' End of script. Logfile hash: b01bbcd0d1, CPU: user 0.03s system 0.00s, MEM: 14.03 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 53% 1x abc (0 sec), 29% 1x show (0 sec), ... make[3]: Leaving directory '/build/yosys-cNltON/yosys-0.15/manual/PRESENTATION_ExSyn' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20220326155523Z)#' PRESENTATION_ExSyn/abc_01.pdf PRESENTATION_ExSyn/memory_01.pdf PRESENTATION_ExSyn/memory_02.pdf PRESENTATION_ExSyn/opt_01.pdf PRESENTATION_ExSyn/opt_02.pdf PRESENTATION_ExSyn/opt_03.pdf PRESENTATION_ExSyn/opt_04.pdf PRESENTATION_ExSyn/proc_01.pdf PRESENTATION_ExSyn/proc_02.pdf PRESENTATION_ExSyn/proc_03.pdf PRESENTATION_ExSyn/techmap_01.pdf + make -C PRESENTATION_ExAdv make[3]: Entering directory '/build/yosys-cNltON/yosys-0.15/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys select.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `select.ys' -- 1. Executing Verilog-2005 frontend: select.v Parsing Verilog input from `select.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 2 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\test.$proc$select.v:7$1'. 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\test.\b' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$8' with positive edge clock. Creating register for signal `\test.\c' using process `\test.$proc$select.v:7$1'. created $dff cell `$procdff$9' with positive edge clock. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `test.$proc$select.v:7$1'. Cleaned up 0 empty switches. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4. Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 1 cells. 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.6. Executing OPT_DFF pass (perform DFF optimizations). 4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. Removed 1 unused cells and 7 unused wires. 4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.9. Rerunning OPT passes. (Maybe there is more to do..) 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \test.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \test. Performed a total of 0 changes. 4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\test'. Removed a total of 0 cells. 4.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \test.. 4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module test. 4.16. Finished OPT passes. (There is nothing left to do.) 5. Generating Graphviz representation of design. Writing dot description to `select.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'select.dot' > 'select.pdf.new' && mv 'select.pdf.new' 'select.pdf' End of script. Logfile hash: 4809312089, CPU: user 0.04s system 0.01s, MEM: 11.71 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 46% 1x show (0 sec), 17% 4x opt_expr (0 sec), ... ../../yosys red_or3x1_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `red_or3x1_test.ys' -- 1. Executing Verilog-2005 frontend: red_or3x1_test.v Parsing Verilog input from `red_or3x1_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: red_or3x1_map.v Parsing Verilog input from `red_or3x1_map.v' to AST representation. Generating RTLIL representation for module `\$reduce_or'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$53153ae57fdb25b25475408a64760d7986ecfb0e\$reduce_or for cells of type $reduce_or. Using template $paramod$fe2472242c070f3b22e97f6c8c19c3569e575d97\$reduce_or for cells of type $reduce_or. Using template $paramod$1a3ccc6b2ad940e0a4ee2fb765a3adeb638fb7f0\$reduce_or for cells of type $reduce_or. No more expansions possible. Removed 0 unused cells and 18 unused wires. 4. Executing SPLITNETS pass (splitting up multi-bit signals). 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend: red_or3x1_cells.v Parsing Verilog input from `red_or3x1_cells.v' to AST representation. Generating RTLIL representation for module `\OR3X1'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `red_or3x1.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'red_or3x1.dot' > 'red_or3x1.pdf.new' && mv 'red_or3x1.pdf.new' 'red_or3x1.pdf' End of script. Logfile hash: 129023a082, CPU: user 0.01s system 0.00s, MEM: 11.75 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 83% 1x show (0 sec), 7% 1x techmap (0 sec), ... ../../yosys sym_mul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `sym_mul_test.ys' -- 1. Executing Verilog-2005 frontend: sym_mul_test.v Parsing Verilog input from `sym_mul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. No more expansions possible. Removed 0 unused cells and 6 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `sym_mul.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'sym_mul.dot' > 'sym_mul.pdf.new' && mv 'sym_mul.pdf.new' 'sym_mul.pdf' End of script. Logfile hash: 772afb568b, CPU: user 0.01s system 0.00s, MEM: 11.39 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 75% 1x show (0 sec), 8% 4x read_verilog (0 sec), ... ../../yosys mymul_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `mymul_test.ys' -- 1. Executing Verilog-2005 frontend: mymul_test.v Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: mymul_map.v Parsing Verilog input from `mymul_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Continuing TECHMAP pass. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\$mul for cells of type $mul. Using template $paramod\MYMUL\WIDTH=32'00000000000000000000000000000010 for cells of type MYMUL. No more expansions possible. Removed 0 unused cells and 10 unused wires. Renaming module \test to \test_mapped. 4. Executing Verilog-2005 frontend: mymul_test.v Parsing Verilog input from `mymul_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 5. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped". 6. Executing FLATTEN pass (flatten design). 7. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 7 cells to SAT database. Import proof-constraint: \trigger = 1'0 Final proof equation: \trigger = 1'0 Solving problem with 107 variables and 283 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ 8. Executing SPLITNETS pass (splitting up multi-bit signals). 9. Generating Graphviz representation of design. Writing dot description to `mymul.dot'. Dumping module test_mapped to page 1. Exec: dot -Tpdf 'mymul.dot' > 'mymul.pdf.new' && mv 'mymul.pdf.new' 'mymul.pdf' End of script. Logfile hash: f23e100602, CPU: user 0.03s system 0.00s, MEM: 12.41 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 62% 1x show (0 sec), 10% 2x clean (0 sec), ... ../../yosys mulshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `mulshift_test.ys' -- 1. Executing Verilog-2005 frontend: mulshift_test.v Parsing Verilog input from `mulshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: sym_mul_map.v Parsing Verilog input from `sym_mul_map.v' to AST representation. Generating RTLIL representation for module `\$mul'. Successfully finished Verilog frontend. 3.2. Executing Verilog-2005 frontend: mulshift_map.v Parsing Verilog input from `mulshift_map.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 3.3. Continuing TECHMAP pass. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul. Using template $paramod$fb3c811cfd9dc2fc74fe40190dfcd365f04584f7\MYMUL for cells of type MYMUL. No more expansions possible. Removed 0 unused cells and 16 unused wires. 4. Generating Graphviz representation of design. 4.1. Executing Verilog-2005 frontend: sym_mul_cells.v Parsing Verilog input from `sym_mul_cells.v' to AST representation. Generating RTLIL representation for module `\MYMUL'. Successfully finished Verilog frontend. 4.2. Continuing show pass. Writing dot description to `mulshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'mulshift.dot' > 'mulshift.pdf.new' && mv 'mulshift.pdf.new' 'mulshift.pdf' End of script. Logfile hash: 891a849ce3, CPU: user 0.03s system 0.01s, MEM: 12.30 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 59% 1x show (0 sec), 13% 3x clean (0 sec), ... ../../yosys addshift_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `addshift_test.ys' -- 1. Executing Verilog-2005 frontend: addshift_test.v Parsing Verilog input from `addshift_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: addshift_map.v Parsing Verilog input from `addshift_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$ba28896eb640c0d0dd7116971c6c5dc347170a6c\$add for cells of type $add. No more expansions possible. Removed 0 unused cells and 7 unused wires. 4. Generating Graphviz representation of design. Writing dot description to `addshift.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'addshift.dot' > 'addshift.pdf.new' && mv 'addshift.pdf.new' 'addshift.pdf' End of script. Logfile hash: d1e94967df, CPU: user 0.01s system 0.01s, MEM: 11.33 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 82% 1x show (0 sec), 6% 1x clean (0 sec), ... ../../yosys macc_simple_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `macc_simple_test.ys' -- 1. Executing Verilog-2005 frontend: macc_simple_test.v Parsing Verilog input from `macc_simple_test.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 3. Generating Graphviz representation of design. 3.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 3.2. Continuing show pass. Writing dot description to `macc_simple_test_00a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00a.dot' > 'macc_simple_test_00a.pdf.new' && mv 'macc_simple_test_00a.pdf.new' 'macc_simple_test_00a.pdf' 4. Executing EXTRACT pass (map subcircuits to cells). 4.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 4.2.4. Executing PROC_INIT pass (extract init attributes). 4.2.5. Executing PROC_ARST pass (detect async resets in processes). 4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). 4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 4.2.8. Executing PROC_DFF pass (convert process syncs to FFs). 4.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.11. Executing OPT_EXPR pass (perform const folding). Optimizing module macc_16_16_32. 4.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 4.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 4.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 4.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$7 -> $add$macc_simple_test.v:5$2 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_simple_xmap.v:5$6 -> $mul$macc_simple_test.v:5$1 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$8 Removed 0 unused cells and 1 unused wires. 5. Generating Graphviz representation of design. 5.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 5.2. Continuing show pass. Writing dot description to `macc_simple_test_00b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_00b.dot' > 'macc_simple_test_00b.pdf.new' && mv 'macc_simple_test_00b.pdf.new' 'macc_simple_test_00b.pdf' 6. Executing Verilog-2005 frontend: macc_simple_test_01.v Parsing Verilog input from `macc_simple_test_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 7. Executing HIERARCHY pass (managing design hierarchy). 7.1. Analyzing design hierarchy.. Top module: \test 7.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 8. Generating Graphviz representation of design. 8.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 8.2. Continuing show pass. Writing dot description to `macc_simple_test_01a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01a.dot' > 'macc_simple_test_01a.pdf.new' && mv 'macc_simple_test_01a.pdf.new' 'macc_simple_test_01a.pdf' 9. Executing EXTRACT pass (map subcircuits to cells). 9.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 9.2. Executing PROC pass (convert processes to netlists). 9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 9.2.4. Executing PROC_INIT pass (extract init attributes). 9.2.5. Executing PROC_ARST pass (detect async resets in processes). 9.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). 9.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 9.2.8. Executing PROC_DFF pass (convert process syncs to FFs). 9.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 9.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 9.2.11. Executing OPT_EXPR pass (perform const folding). Optimizing module macc_16_16_32. 9.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 9.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 9.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 1 matches. 9.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$18 -> $add$macc_simple_test_01.v:5$13 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$17 -> $mul$macc_simple_test_01.v:5$11 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$19 Removed 0 unused cells and 1 unused wires. 10. Generating Graphviz representation of design. 10.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 10.2. Continuing show pass. Writing dot description to `macc_simple_test_01b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_01b.dot' > 'macc_simple_test_01b.pdf.new' && mv 'macc_simple_test_01b.pdf.new' 'macc_simple_test_01b.pdf' 11. Executing Verilog-2005 frontend: macc_simple_test_02.v Parsing Verilog input from `macc_simple_test_02.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 12. Executing HIERARCHY pass (managing design hierarchy). 12.1. Analyzing design hierarchy.. Top module: \test 12.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 13. Generating Graphviz representation of design. 13.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 13.2. Continuing show pass. Writing dot description to `macc_simple_test_02a.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02a.dot' > 'macc_simple_test_02a.pdf.new' && mv 'macc_simple_test_02a.pdf.new' 'macc_simple_test_02a.pdf' 14. Executing EXTRACT pass (map subcircuits to cells). 14.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 14.2. Executing PROC pass (convert processes to netlists). 14.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 14.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 14.2.4. Executing PROC_INIT pass (extract init attributes). 14.2.5. Executing PROC_ARST pass (detect async resets in processes). 14.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). 14.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). 14.2.8. Executing PROC_DFF pass (convert process syncs to FFs). 14.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 14.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 14.2.11. Executing OPT_EXPR pass (perform const folding). Optimizing module macc_16_16_32. 14.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \macc_16_16_32.. Removed 0 unused cells and 1 unused wires. 14.4. Creating graphs for SubCircuit library. Creating needle graph needle_macc_16_16_32. Creating haystack graph haystack_test. 14.5. Running solver from SubCircuit library. Solving for needle_macc_16_16_32 in haystack_test. Found 2 matches. 14.6. Substitute SubCircuits with cells. Match #0: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$24 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$23 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$30 Match #1: (needle_macc_16_16_32 in haystack_test) $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$25 \A:\A \B:\B \Y:\Y $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$22 \A:\A \B:\B \Y:\Y new cell: $extract$\macc_16_16_32$31 Removed 0 unused cells and 2 unused wires. 15. Generating Graphviz representation of design. 15.1. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 15.2. Continuing show pass. Writing dot description to `macc_simple_test_02b.dot'. Dumping module test to page 1. Exec: dot -Tpdf 'macc_simple_test_02b.dot' > 'macc_simple_test_02b.pdf.new' && mv 'macc_simple_test_02b.pdf.new' 'macc_simple_test_02b.pdf' 16. Executing Verilog-2005 frontend: macc_simple_xmap.v Parsing Verilog input from `macc_simple_xmap.v' to AST representation. Generating RTLIL representation for module `\macc_16_16_32'. Successfully finished Verilog frontend. 17. Executing HIERARCHY pass (managing design hierarchy). 17.1. Analyzing design hierarchy.. Top module: \macc_16_16_32 17.2. Analyzing design hierarchy.. Top module: \macc_16_16_32 Removed 0 unused modules. Removed 0 unused cells and 1 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_simple_xmap.dot'. Dumping module macc_16_16_32 to page 1. Exec: dot -Tpdf 'macc_simple_xmap.dot' > 'macc_simple_xmap.pdf.new' && mv 'macc_simple_xmap.pdf.new' 'macc_simple_xmap.pdf' End of script. Logfile hash: 87ef763ab0, CPU: user 0.05s system 0.00s, MEM: 11.64 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 86% 7x show (0 sec), 4% 7x clean (0 sec), ... ../../yosys macc_xilinx_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `macc_xilinx_test.ys' -- 1. Executing Verilog-2005 frontend: macc_xilinx_test.v Parsing Verilog input from `macc_xilinx_test.v' to AST representation. Generating RTLIL representation for module `\test1'. Generating RTLIL representation for module `\test2'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `$__mul_wrapper'. Generating RTLIL representation for module `$__add_wrapper'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 4. Executing HIERARCHY pass (managing design hierarchy). Removed 0 unused cells and 2 unused wires. 5. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1a.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1a.dot' > 'macc_xilinx_test1a.pdf.new' && mv 'macc_xilinx_test1a.pdf.new' 'macc_xilinx_test1a.pdf' 6. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2a.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2a.dot' > 'macc_xilinx_test2a.pdf.new' && mv 'macc_xilinx_test2a.pdf.new' 'macc_xilinx_test2a.pdf' 7. Executing TECHMAP pass (map to technology primitives). 7.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 7.2. Continuing TECHMAP pass. Using template $paramod$cb31b7e2c27e209b1e5fc8ca3c6ec22d65eb4c07\mul_swap_ports for cells of type $mul. No more expansions possible. Removed 0 unused cells and 8 unused wires. 8. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1b.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1b.dot' > 'macc_xilinx_test1b.pdf.new' && mv 'macc_xilinx_test1b.pdf.new' 'macc_xilinx_test1b.pdf' 9. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2b.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2b.dot' > 'macc_xilinx_test2b.pdf.new' && mv 'macc_xilinx_test2b.pdf.new' 'macc_xilinx_test2b.pdf' 10. Executing TECHMAP pass (map to technology primitives). 10.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 10.2. Continuing TECHMAP pass. Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\mul_wrap for cells of type $mul. Using template $paramod$48197a291a9e3825142389e9d2e41385cae2467c\mul_wrap for cells of type $mul. Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\add_wrap for cells of type $add. No more expansions possible. 11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells). Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y } Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y } Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y } Removed 0 unused cells and 56 unused wires. 12. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1c.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1c.dot' > 'macc_xilinx_test1c.pdf.new' && mv 'macc_xilinx_test1c.pdf.new' 'macc_xilinx_test1c.pdf' 13. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2c.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2c.dot' > 'macc_xilinx_test2c.pdf.new' && mv 'macc_xilinx_test2c.pdf.new' 'macc_xilinx_test2c.pdf' 14. Executing Verilog-2005 frontend: macc_xilinx_xmap.v Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation. Generating RTLIL representation for module `\DSP48_MACC'. Successfully finished Verilog frontend. 15. Executing TECHMAP pass (map to technology primitives). 15.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation. Generating RTLIL representation for module `\mul_swap_ports'. Successfully finished Verilog frontend. 15.2. Continuing TECHMAP pass. No more expansions possible. 16. Executing TECHMAP pass (map to technology primitives). 16.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation. Generating RTLIL representation for module `\mul_wrap'. Generating RTLIL representation for module `\add_wrap'. Successfully finished Verilog frontend. 16.2. Continuing TECHMAP pass. Using template $paramod$81421da67e3cf07e7ac8b39f28efc75ee750e82a\mul_wrap for cells of type $mul. Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\add_wrap for cells of type $add. No more expansions possible. Removed 0 unused cells and 17 unused wires. 17. Executing EXTRACT pass (map subcircuits to cells). 17.1. Creating graphs for SubCircuit library. Creating needle graph needle_DSP48_MACC. Creating haystack graph haystack_$__add_wrapper. Creating haystack graph haystack_$__mul_wrapper. Creating haystack graph haystack_DSP48_MACC. Creating haystack graph haystack_test1. Creating haystack graph haystack_test2. 17.2. Running solver from SubCircuit library. Solving for needle_DSP48_MACC in haystack_$__add_wrapper. Solving for needle_DSP48_MACC in haystack_$__mul_wrapper. Solving for needle_DSP48_MACC in haystack_DSP48_MACC. Solving for needle_DSP48_MACC in haystack_test1. Solving for needle_DSP48_MACC in haystack_test2. Found 3 matches. 17.3. Substitute SubCircuits with cells. Match #0: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$35 Match #1: (needle_DSP48_MACC in haystack_test1) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$36 Match #2: (needle_DSP48_MACC in haystack_test2) $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y $const$0 -> $const$0 \Y:\Y $const$1 -> $const$1 \Y:\Y $const$x -> $const$x \Y:\Y $const$z -> $const$z \Y:\Y $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y new cell: $extract$\DSP48_MACC$37 Removed 0 unused cells and 6 unused wires. 18. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1d.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1d.dot' > 'macc_xilinx_test1d.pdf.new' && mv 'macc_xilinx_test1d.pdf.new' 'macc_xilinx_test1d.pdf' 19. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2d.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2d.dot' > 'macc_xilinx_test2d.pdf.new' && mv 'macc_xilinx_test2d.pdf.new' 'macc_xilinx_test2d.pdf' 20. Executing TECHMAP pass (map to technology primitives). 20.1. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation. Generating RTLIL representation for module `\$__mul_wrapper'. Generating RTLIL representation for module `\$__add_wrapper'. Successfully finished Verilog frontend. 20.2. Continuing TECHMAP pass. Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\$__mul_wrapper for cells of type $__mul_wrapper. Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\$__add_wrapper for cells of type $__add_wrapper. No more expansions possible. Removed 0 unused cells and 14 unused wires. 21. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test1e.dot'. Dumping module test1 to page 1. Exec: dot -Tpdf 'macc_xilinx_test1e.dot' > 'macc_xilinx_test1e.pdf.new' && mv 'macc_xilinx_test1e.pdf.new' 'macc_xilinx_test1e.pdf' 22. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_test2e.dot'. Dumping module test2 to page 1. Exec: dot -Tpdf 'macc_xilinx_test2e.dot' > 'macc_xilinx_test2e.pdf.new' && mv 'macc_xilinx_test2e.pdf.new' 'macc_xilinx_test2e.pdf' 23. Generating Graphviz representation of design. Writing dot description to `macc_xilinx_xmap.dot'. Dumping module DSP48_MACC to page 1. Exec: dot -Tpdf 'macc_xilinx_xmap.dot' > 'macc_xilinx_xmap.pdf.new' && mv 'macc_xilinx_xmap.pdf.new' 'macc_xilinx_xmap.pdf' End of script. Logfile hash: 30f24e3366, CPU: user 0.07s system 0.01s, MEM: 12.73 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 83% 11x show (0 sec), 7% 12x clean (0 sec), ... make[3]: Leaving directory '/build/yosys-cNltON/yosys-0.15/manual/PRESENTATION_ExAdv' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20220326155523Z)#' PRESENTATION_ExAdv/addshift.pdf PRESENTATION_ExAdv/macc_simple_test_00a.pdf PRESENTATION_ExAdv/macc_simple_test_00b.pdf PRESENTATION_ExAdv/macc_simple_test_01a.pdf PRESENTATION_ExAdv/macc_simple_test_01b.pdf PRESENTATION_ExAdv/macc_simple_test_02a.pdf PRESENTATION_ExAdv/macc_simple_test_02b.pdf PRESENTATION_ExAdv/macc_simple_xmap.pdf PRESENTATION_ExAdv/macc_xilinx_test1a.pdf PRESENTATION_ExAdv/macc_xilinx_test1b.pdf PRESENTATION_ExAdv/macc_xilinx_test1c.pdf PRESENTATION_ExAdv/macc_xilinx_test1d.pdf PRESENTATION_ExAdv/macc_xilinx_test1e.pdf PRESENTATION_ExAdv/macc_xilinx_test2a.pdf PRESENTATION_ExAdv/macc_xilinx_test2b.pdf PRESENTATION_ExAdv/macc_xilinx_test2c.pdf PRESENTATION_ExAdv/macc_xilinx_test2d.pdf PRESENTATION_ExAdv/macc_xilinx_test2e.pdf PRESENTATION_ExAdv/macc_xilinx_xmap.pdf PRESENTATION_ExAdv/mulshift.pdf PRESENTATION_ExAdv/mymul.pdf PRESENTATION_ExAdv/red_or3x1.pdf PRESENTATION_ExAdv/select.pdf PRESENTATION_ExAdv/sym_mul.pdf + make -C PRESENTATION_ExOth make[3]: Entering directory '/build/yosys-cNltON/yosys-0.15/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys scrambler.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `scrambler.ys' -- 1. Executing Verilog-2005 frontend: scrambler.v Parsing Verilog input from `scrambler.v' to AST representation. Generating RTLIL representation for module `\scrambler'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 3. Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler. Removed a total of 0 dead cases. 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 2 assignments to connections. 3.4. Executing PROC_INIT pass (extract init attributes). 3.5. Executing PROC_ARST pass (detect async resets in processes). 3.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'. 1/1: $1\xs[31:0] 3.7. Executing PROC_DLATCH pass (convert process syncs to latches). 3.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$12' with positive edge clock. Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'. created $dff cell `$procdff$13' with positive edge clock. 3.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'. Removing empty process `scrambler.$proc$scrambler.v:6$1'. Cleaned up 1 empty switch. 3.11. Executing OPT_EXPR pass (perform const folding). Optimizing module scrambler. Removed 0 unused cells and 5 unused wires. 4. Executing SUBMOD pass (moving cells to submodules as requested). 4.1. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \scrambler.. 4.2. Continuing SUBMOD pass. Creating submodule xorshift32 (\xorshift32) of module \scrambler. signal $xor$scrambler.v:10$5_Y: internal signal $shl$scrambler.v:11$6_Y: internal signal $0\xs[31:0]: output \n1 signal $1\xs[31:0]: input \n2 signal $xor$scrambler.v:9$3_Y: internal signal $shr$scrambler.v:10$4_Y: internal cell $xor$scrambler.v:9$3 ($xor) cell $xor$scrambler.v:11$7 ($xor) cell $xor$scrambler.v:10$5 ($xor) 5. Generating Graphviz representation of design. Writing dot description to `scrambler_p01.dot'. Dumping module scrambler to page 1. Exec: dot -Tpdf 'scrambler_p01.dot' > 'scrambler_p01.pdf.new' && mv 'scrambler_p01.pdf.new' 'scrambler_p01.pdf' 6. Generating Graphviz representation of design. Writing dot description to `scrambler_p02.dot'. Dumping module xorshift32 to page 1. Exec: dot -Tpdf 'scrambler_p02.dot' > 'scrambler_p02.pdf.new' && mv 'scrambler_p02.pdf.new' 'scrambler_p02.pdf' echo on yosys> cd xorshift32 yosys [xorshift32]> rename n2 in Renaming wire n2 to in in module xorshift32. yosys [xorshift32]> rename n1 out Renaming wire n1 to out in module xorshift32. yosys [xorshift32]> eval -set in 1 -show out 7. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 270369. yosys [xorshift32]> eval -set in 270369 -show out 8. Executing EVAL pass (evaluate the circuit given an input). Eval result: \out = 67634689. yosys [xorshift32]> sat -set out 632435482 9. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Import set-constraint: \out = 632435482 Final constraint equation: \out = 632435482 Imported 3 cells to SAT database. Solving problem with 665 variables and 1735 clauses.. SAT solving finished - model found: Signal Name Dec Hex Bin --------------- ----------- --------- ----------------------------------- \in 745495504 2c6f5bd0 00101100011011110101101111010000 \out 632435482 25b2331a 00100101101100100011001100011010 End of script. Logfile hash: 494bb4dd7b, CPU: user 0.01s system 0.00s, MEM: 12.42 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 78% 2x show (0 sec), 6% 1x sat (0 sec), ... ../../yosys -l equiv.log_new equiv.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `equiv.ys' -- 1. Executing Verilog-2005 frontend: ../PRESENTATION_ExSyn/techmap_01.v Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01.v' to AST representation. Generating RTLIL representation for module `\test'. Successfully finished Verilog frontend. 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \test 2.2. Analyzing design hierarchy.. Top module: \test Removed 0 unused modules. Renaming module \test to \test_mapped. 3. Executing TECHMAP pass (map to technology primitives). 3.1. Executing Verilog-2005 frontend: ../PRESENTATION_ExSyn/techmap_01_map.v Parsing Verilog input from `../PRESENTATION_ExSyn/techmap_01_map.v' to AST representation. Generating RTLIL representation for module `\$add'. Successfully finished Verilog frontend. 3.2. Continuing TECHMAP pass. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add. No more expansions possible. 4. Executing MITER pass (creating miter circuit). Creating miter cell "miter" with gold cell "test_orig" and gate cell "test_mapped". 5. Executing FLATTEN pass (flatten design). 6. Executing SAT pass (solving SAT problems in the circuit). Setting up SAT problem: Final constraint equation: { } = { } Imported 7 cells to SAT database. Import proof for assert: $auto$miter.cc:207:create_miter_equiv$6 when 1'1. Import show expression: \in_b Import show expression: \in_a Import show expression: \trigger Import show expression: \gate_y Import show expression: \gold_y Solving problem with 945 variables and 2505 clauses.. SAT proof finished - no model found: SUCCESS! /$$$$$$ /$$$$$$$$ /$$$$$$$ /$$__ $$ | $$_____/ | $$__ $$ | $$ \ $$ | $$ | $$ \ $$ | $$ | $$ | $$$$$ | $$ | $$ | $$ | $$ | $$__/ | $$ | $$ | $$/$$ $$ | $$ | $$ | $$ | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$ \____ $$$|__/|________/|__/|_______/|__/ \__/ End of script. Logfile hash: d222a819ed, CPU: user 0.01s system 0.00s, MEM: 12.52 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 76% 1x sat (0 sec), 13% 1x techmap (0 sec), ... mv equiv.log_new equiv.log ../../yosys -l axis_test.log_new axis_test.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.15 (git sha1 2156e20) -- Executing script file `axis_test.ys' -- 1. Executing Verilog-2005 frontend: axis_master.v Parsing SystemVerilog input from `axis_master.v' to AST representation. Generating RTLIL representation for module `\axis_master'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: axis_test.v Parsing SystemVerilog input from `axis_test.v' to AST representation. Generating RTLIL representation for module `\axis_test'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master 3.2. Analyzing design hierarchy.. Top module: \axis_test Used module: \axis_master Removed 0 unused modules. Module axis_test directly or indirectly contains formal properties -> setting "keep" attribute. Mapping positional arguments of cell axis_test.uut (axis_master). 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 2 switch rules as full_case in process $proc$axis_master.v:7$1 in module axis_master. Removed a total of 0 dead cases. 4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 14 assignments to connections. 4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\axis_test.$proc$axis_test.v:0$98'. Set init value: $formal$axis_test.v:22$23_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$96'. Set init value: $formal$axis_test.v:21$22_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$94'. Set init value: $formal$axis_test.v:20$21_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$92'. Set init value: $formal$axis_test.v:19$20_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$90'. Set init value: $formal$axis_test.v:18$19_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$88'. Set init value: $formal$axis_test.v:17$18_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$86'. Set init value: $formal$axis_test.v:16$17_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$84'. Set init value: $formal$axis_test.v:15$16_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$82'. Set init value: $formal$axis_test.v:14$15_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:0$80'. Set init value: $formal$axis_test.v:13$14_EN = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:7$79'. Set init value: \aresetn = 1'0 Found init rule in `\axis_test.$proc$axis_test.v:6$78'. Set init value: \counter = 0 4.5. Executing PROC_ARST pass (detect async resets in processes). 4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\axis_test.$proc$axis_test.v:0$98'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$96'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$94'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$92'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$90'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$88'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$86'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$84'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$82'. Creating decoders for process `\axis_test.$proc$axis_test.v:0$80'. Creating decoders for process `\axis_test.$proc$axis_test.v:7$79'. Creating decoders for process `\axis_test.$proc$axis_test.v:6$78'. Creating decoders for process `\axis_test.$proc$axis_test.v:11$24'. 1/21: $0$formal$axis_test.v:13$14_EN[0:0]$26 2/21: $0$formal$axis_test.v:13$14_CHECK[0:0]$25 3/21: $0$formal$axis_test.v:14$15_EN[0:0]$28 4/21: $0$formal$axis_test.v:14$15_CHECK[0:0]$27 5/21: $0$formal$axis_test.v:15$16_EN[0:0]$30 6/21: $0$formal$axis_test.v:15$16_CHECK[0:0]$29 7/21: $0$formal$axis_test.v:16$17_EN[0:0]$32 8/21: $0$formal$axis_test.v:16$17_CHECK[0:0]$31 9/21: $0$formal$axis_test.v:17$18_EN[0:0]$34 10/21: $0$formal$axis_test.v:17$18_CHECK[0:0]$33 11/21: $0$formal$axis_test.v:18$19_EN[0:0]$36 12/21: $0$formal$axis_test.v:18$19_CHECK[0:0]$35 13/21: $0$formal$axis_test.v:19$20_EN[0:0]$38 14/21: $0$formal$axis_test.v:19$20_CHECK[0:0]$37 15/21: $0$formal$axis_test.v:20$21_EN[0:0]$40 16/21: $0$formal$axis_test.v:20$21_CHECK[0:0]$39 17/21: $0$formal$axis_test.v:21$22_EN[0:0]$42 18/21: $0$formal$axis_test.v:21$22_CHECK[0:0]$41 19/21: $0$formal$axis_test.v:22$23_EN[0:0]$44 20/21: $0$formal$axis_test.v:22$23_CHECK[0:0]$43 21/21: $0\counter[31:0] Creating decoders for process `\axis_master.$proc$axis_master.v:7$1'. 1/4: $2\state[31:0] 2/4: $1\state[31:0] 3/4: $0\tdata[7:0] 4/4: $0\tvalid[0:0] 4.7. Executing PROC_DLATCH pass (convert process syncs to latches). 4.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\axis_test.\aresetn' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$209' with positive edge clock. Creating register for signal `\axis_test.\counter' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$210' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$211' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:13$14_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$212' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$213' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:14$15_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$214' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$215' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:15$16_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$216' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$217' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:16$17_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$218' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$219' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:17$18_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$220' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$221' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:18$19_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$222' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$223' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:19$20_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$224' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$225' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:20$21_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$226' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$227' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:21$22_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$228' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_CHECK' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$229' with positive edge clock. Creating register for signal `\axis_test.$formal$axis_test.v:22$23_EN' using process `\axis_test.$proc$axis_test.v:11$24'. created $dff cell `$procdff$230' with positive edge clock. Creating register for signal `\axis_master.\tvalid' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$231' with positive edge clock. Creating register for signal `\axis_master.\tdata' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$232' with positive edge clock. Creating register for signal `\axis_master.\state' using process `\axis_master.$proc$axis_master.v:7$1'. created $dff cell `$procdff$233' with positive edge clock. 4.9. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `axis_test.$proc$axis_test.v:0$98'. Removing empty process `axis_test.$proc$axis_test.v:0$96'. Removing empty process `axis_test.$proc$axis_test.v:0$94'. Removing empty process `axis_test.$proc$axis_test.v:0$92'. Removing empty process `axis_test.$proc$axis_test.v:0$90'. Removing empty process `axis_test.$proc$axis_test.v:0$88'. Removing empty process `axis_test.$proc$axis_test.v:0$86'. Removing empty process `axis_test.$proc$axis_test.v:0$84'. Removing empty process `axis_test.$proc$axis_test.v:0$82'. Removing empty process `axis_test.$proc$axis_test.v:0$80'. Removing empty process `axis_test.$proc$axis_test.v:7$79'. Removing empty process `axis_test.$proc$axis_test.v:6$78'. Found and cleaned up 11 empty switches in `\axis_test.$proc$axis_test.v:11$24'. Removing empty process `axis_test.$proc$axis_test.v:11$24'. Found and cleaned up 4 empty switches in `\axis_master.$proc$axis_master.v:7$1'. Removing empty process `axis_master.$proc$axis_master.v:7$1'. Cleaned up 15 empty switches. 4.11. Executing OPT_EXPR pass (perform const folding). Optimizing module axis_test. Optimizing module axis_master. 5. Executing FLATTEN pass (flatten design). Deleting now unused module axis_master. Removed 1 unused cells and 92 unused wires. 6. Executing SAT pass (solving SAT problems in the circuit). Setting up time step 1: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import set-constraint from init attribute: $formal$axis_test.v:13$14_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:14$15_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:15$16_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:16$17_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:17$18_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:18$19_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:19$20_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:20$21_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:21$22_EN = 1'0 Import set-constraint from init attribute: $formal$axis_test.v:22$23_EN = 1'0 Import set-constraint from init attribute: \aresetn = 1'0 Import set-constraint from init attribute: \counter = 0 Final init constraint equation: { \counter \aresetn $formal$axis_test.v:22$23_EN $formal$axis_test.v:21$22_EN $formal$axis_test.v:20$21_EN $formal$axis_test.v:19$20_EN $formal$axis_test.v:18$19_EN $formal$axis_test.v:17$18_EN $formal$axis_test.v:16$17_EN $formal$axis_test.v:15$16_EN $formal$axis_test.v:14$15_EN $formal$axis_test.v:13$14_EN } = 43'0000000000000000000000000000000000000000000 Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 2: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 3: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 4: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 5: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 6: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 7: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 8: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 9: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 10: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 11: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 12: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 13: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 14: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 15: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 16: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 17: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 18: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 19: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 20: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 21: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 22: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 23: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 24: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 25: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 26: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 27: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 28: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 29: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 30: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 31: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 32: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 33: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 34: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 35: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 36: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 37: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 38: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 39: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 40: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 41: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 42: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 43: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 44: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 45: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 46: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 47: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 48: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 49: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Setting up time step 50: Final constraint equation: { } = { } Imported 117 cells to SAT database. Import proof for assert: $formal$axis_test.v:13$14_CHECK when $formal$axis_test.v:13$14_EN. Import proof for assert: $formal$axis_test.v:14$15_CHECK when $formal$axis_test.v:14$15_EN. Import proof for assert: $formal$axis_test.v:15$16_CHECK when $formal$axis_test.v:15$16_EN. Import proof for assert: $formal$axis_test.v:16$17_CHECK when $formal$axis_test.v:16$17_EN. Import proof for assert: $formal$axis_test.v:17$18_CHECK when $formal$axis_test.v:17$18_EN. Import proof for assert: $formal$axis_test.v:18$19_CHECK when $formal$axis_test.v:18$19_EN. Import proof for assert: $formal$axis_test.v:19$20_CHECK when $formal$axis_test.v:19$20_EN. Import proof for assert: $formal$axis_test.v:20$21_CHECK when $formal$axis_test.v:20$21_EN. Import proof for assert: $formal$axis_test.v:21$22_CHECK when $formal$axis_test.v:21$22_EN. Import proof for assert: $formal$axis_test.v:22$23_CHECK when $formal$axis_test.v:22$23_EN. Solving problem with 135995 variables and 381779 clauses.. SAT proof finished - model found: FAIL! ______ ___ ___ _ _ _ _ (_____ \ / __) / __) (_) | | | | _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | | | ____/ ___) _ \ / _ (_ __) (_ __|____ | | || ___ |/ _ |_| | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ |_| |_| \___/ \___/ |_| |_| \_____|_|\_)_____)\____|_| Time Signal Name Dec Hex Bin ---- ------------------------------------ ----------- --------- ----------------------------------- init $formal$axis_test.v:13$14_CHECK 0 0 0 init $formal$axis_test.v:13$14_EN 0 0 0 init $formal$axis_test.v:14$15_CHECK 0 0 0 init $formal$axis_test.v:14$15_EN 0 0 0 init $formal$axis_test.v:15$16_CHECK 0 0 0 init $formal$axis_test.v:15$16_EN 0 0 0 init $formal$axis_test.v:16$17_CHECK 0 0 0 init $formal$axis_test.v:16$17_EN 0 0 0 init $formal$axis_test.v:17$18_CHECK 0 0 0 init $formal$axis_test.v:17$18_EN 0 0 0 init $formal$axis_test.v:18$19_CHECK 0 0 0 init $formal$axis_test.v:18$19_EN 0 0 0 init $formal$axis_test.v:19$20_CHECK 0 0 0 init $formal$axis_test.v:19$20_EN 0 0 0 init $formal$axis_test.v:20$21_CHECK 0 0 0 init $formal$axis_test.v:20$21_EN 0 0 0 init $formal$axis_test.v:21$22_CHECK 0 0 0 init $formal$axis_test.v:21$22_EN 0 0 0 init $formal$axis_test.v:22$23_CHECK 0 0 0 init $formal$axis_test.v:22$23_EN 0 0 0 init \aresetn 0 0 0 init \counter 0 0 00000000000000000000000000000000 init \uut.state 0 0 00000000000000000000000000000000 init \uut.tdata 64 40 01000000 init \uut.tvalid 1 1 1 End of script. Logfile hash: b0d6f79805, CPU: user 1.81s system 0.09s, MEM: 127.34 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 99% 1x sat (1 sec), 0% 3x read_verilog (0 sec), ... mv axis_test.log_new axis_test.log make[3]: Leaving directory '/build/yosys-cNltON/yosys-0.15/manual/PRESENTATION_ExOth' + sed -i 's#/CreationDate (D:[^)]\+)#/CreationDate (D:20220326155523Z)#' PRESENTATION_ExOth/scrambler_p01.pdf PRESENTATION_ExOth/scrambler_p02.pdf + make -C PRESENTATION_Prog make[3]: Entering directory '/build/yosys-cNltON/yosys-0.15/manual' make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make rule. ../../yosys-config --exec --cxx -g -O2 -fstack-protector-strong -Wformat -Werror=format-security -Wall -Wextra -ggdb -I../../share/include -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs my_cmd.cc: In member function ‘virtual void {anonymous}::MyPass::execute(std::vector >, Yosys::RTLIL::Design*)’: my_cmd.cc:17:26: warning: format ‘%zd’ expects argument of type ‘signed size_t’, but argument 3 has type ‘int’ [-Wformat=] 17 | log(" %s (%zd wires, %zd cells)\n", log_id(mod), | ~~^ | | | long int | %d 18 | GetSize(mod->wires()), GetSize(mod->cells())); | ~~~~~~~~~~~~~~~~~~~~~ | | | int my_cmd.cc:17:37: warning: format ‘%zd’ expects argument of type ‘signed size_t’, but argument 4 has type ‘int’ [-Wformat=] 17 | log(" %s (%zd wires, %zd cells)\n", log_id(mod), | ~~^ | | | long int | %d 18 | GetSize(mod->wires()), GetSize(mod->cells())); | ~~~~~~~~~~~~~~~~~~~~~ | | | int ../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v -- Parsing `absval_ref.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: absval_ref.v Parsing Verilog input from `absval_ref.v' to AST representation. Storing AST representation for module `$abstract\absval_ref'. Successfully finished Verilog frontend. -- Running command `my_cmd foo bar' -- Arguments to my_cmd: my_cmd foo bar Modules in current design: $abstract\absval_ref (0 wires, 0 cells) End of script. Logfile hash: a25069ff9d, CPU: user 0.00s system 0.00s, MEM: 11.53 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 96% 2x read_verilog (0 sec), 1% 1x my_cmd (0 sec), ... mv test0.log_new test0.log ../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v -- Parsing `absval_ref.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: absval_ref.v Parsing Verilog input from `absval_ref.v' to AST representation. Storing AST representation for module `$abstract\absval_ref'. Successfully finished Verilog frontend. -- Running command `clean; test1; dump' -- Name of this module: absval autoidx 4 module \absval wire width 4 $auto$my_cmd.cc:41:execute$1 wire width 4 output 2 \y wire width 4 input 1 \a cell $mux $auto$my_cmd.cc:43:execute$3 parameter \WIDTH 4 connect \Y \y connect \S \a [3] connect \B $auto$my_cmd.cc:41:execute$1 connect \A \a end cell $neg $auto$my_cmd.cc:42:execute$2 parameter \Y_WIDTH 4 parameter \A_WIDTH 4 parameter \A_SIGNED 1 connect \Y $auto$my_cmd.cc:41:execute$1 connect \A \a end end attribute \cells_not_processed 1 attribute \src "absval_ref.v:1.1-3.10" module $abstract\absval_ref end End of script. Logfile hash: 01cda1039c, CPU: user 0.00s system 0.00s, MEM: 11.63 MB peak Yosys 0.15 (git sha1 2156e20) Time spent: 73% 1x clean (0 sec), 19% 2x read_verilog (0 sec), ... mv test1.log_new test1.log ../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v -- Parsing `sigmap_test.v' using frontend ` -vlog2k' -- 1. Executing Verilog-2005 frontend: sigmap_test.v Parsing Verilog input from `sigmap_test.v' to AST representation. Storing AST representation for module `$abstract\test'. Successfully finished Verilog frontend. -- Running command `hierarchy -top test; test2' -- 2. Executing HIERARCHY pass (managing design hierarchy). 3. Executing AST frontend in derive mode using pre-parsed AST for module `\test'. Generating RTLIL representation for module `\test'. 3.1. Analyzing design hierarchy.. Top module: \test 3.2. Analyzing design hierarchy.. Top module: \test Removing unused module `$abstract\test'. Removed 1 unused modules. 0 0 0 1 1 1 Mapped signal x: \a 4. Doing important stuff! Log message #0. Log message #1. Log message #2. Log message #3. Log message #4. Log message #5. Log message #6. Log message #7. Log message #8. Log message #9. End of script. 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Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [83 <./PRESENTATION_ExSyn/abc_01.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [84] (./presentation.vrb Overfull \hbox (12.91054pt too wide) in paragraph at lines 6--7 [][][][][][][][][][][][][][][] Overfull \hbox (30.19075pt too wide) in paragraph at lines 24--25 [][][][][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (35.95082pt too wide) in paragraph at lines 28--29 [][][][][][][][][][][][][][][][][][][][][][][][][][] Overfull \hbox (44.59093pt too wide) in paragraph at lines 29--31 [][][][][][][][][][][][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [85] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [86]) (./PRESENTATION_ExAdv.tex Overfull \hbox (5.77223pt too wide) has occurred while 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(./PRESENTATION_ExAdv/mymul_map.v Overfull \hbox (9.76546pt too wide) in paragraph at lines 6--8 [][][][][][][][][][][][][][][][][][] ) (./PRESENTATION_ExAdv/mymul_test.v) (./PRESENTATION_ExAdv/mymul_test.ys) (./PRESENTATION_ExAdv/mymul_test.ys consecutive: ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [106 <./PRESENTATION_ExAdv/mymul.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [107] (./PRESENTATION_ExAdv/mulshift_map.v Overfull \hbox (34.2463pt too wide) in paragraph at lines 16--17 [][][][][][][][][][][][][][][][][][][][] Overfull \hbox (34.2463pt too wide) in paragraph at lines 20--21 [][][][][][][][][][][][][][][][][][][][] ) (./PRESENTATION_ExAdv/mulshift_test.v) (./PRESENTATION_ExAdv/mulshift_test.ys ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [108 <./PRESENTATION_ExAdv/mulshift.pdf>] Overfull \hbox (5.77223pt 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(./PRESENTATION_ExAdv/macc_simple_test.v) (./PRESENTATION_ExAdv/macc_simple_xmap.v)) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [115 <./PRESENTATION_ExAdv/macc_simple_test_00a.pdf> <./PRESENTATION_ExAdv/macc _simple_test_00b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_00b.pdf): PDF inclusion: multiple pdfs with page group included in a single page >] (./presentation.vrb (./PRESENTATION_ExAdv/macc_simple_test_01.v) Underfull \hbox (badness 10000) detected at line 3 []| (./PRESENTATION_ExAdv/macc_simple_test_02.v) Underfull \hbox (badness 10000) detected at line 4 []| ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [116 <./PRESENTATION_ExAdv/macc_simple_test_01a.pdf> <./PRESENTATION_ExAdv/macc _simple_test_02a.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_02a.pdf): PDF inclusion: multiple pdfs with page group included in a single page > <./PRESENTATION_ExAdv/macc_simple_test_01b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_01b.pdf): PDF inclusion: multiple pdfs with page group included in a single page > <./PRESENTATION_ExAdv/macc_simple_test_02b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_simple_test_02b.pdf): PDF inclusion: multiple pdfs with page group included in a single page >] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [117] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_swap_map.v) (./PRESENTATION_ExAdv/macc_xilinx_swap_map.v consecutive: )) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [118] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_wrap_map.v Overfull \hbox (2.21822pt too wide) in paragraph at lines 19--21 [][][][][][][][][][][][][][][][][] ) (./PRESENTATION_ExAdv/macc_xilinx_wrap_map.v consecutive: )) Overfull \vbox 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(./PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v consecutive: )) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [123] (./presentation.vrb (./PRESENTATION_ExAdv/macc_xilinx_test.v) Underfull \hbox (badness 10000) detected at line 4 []| (./PRESENTATION_ExAdv/macc_xilinx_test.v consecutive: ) Underfull \hbox (badness 10000) detected at line 5 []| Overfull \hbox (84.2987pt too wide) in paragraph at lines 10--11 [][][][][][][][] Overfull \hbox (26.69807pt too wide) in paragraph at lines 11--12 [][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [124 <./PRESENTATION_ExAdv/macc_xilinx_test1a.pdf> <./PRESENTATION_ExAdv/macc_x ilinx_test2a.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_xilinx_test2a.pdf): PD F inclusion: multiple pdfs with page group included in a single page >] (./presentation.vrb Overfull \hbox (99.65887pt too wide) in paragraph at lines 10--11 [][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [125 <./PRESENTATION_ExAdv/macc_xilinx_test1b.pdf> <./PRESENTATION_ExAdv/macc_x ilinx_test2b.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExAdv/macc_xilinx_test2b.pdf): PD F inclusion: multiple pdfs with page group included in a single page >] (./presentation.vrb Overfull \hbox (7.49786pt too wide) in paragraph at lines 10--11 [][][][][][][][][][] Overfull \hbox (7.49786pt too wide) in paragraph at lines 11--12 [][][][][][][][] Overfull \hbox (7.49786pt too wide) in paragraph at lines 12--13 [][][][][][][][][] Overfull \hbox (11.3379pt too wide) in paragraph at lines 13--14 [][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [126 <./PRESENTATION_ExAdv/macc_xilinx_test1c.pdf>] (./presentation.vrb Overfull \hbox (7.49786pt too wide) in paragraph at lines 10--11 [][][][][][][][][][] Overfull \hbox (7.49786pt too wide) in paragraph at lines 11--12 [][][][][][][][] Overfull \hbox (7.49786pt too wide) in paragraph at lines 12--13 [][][][][][][][][] Overfull \hbox (11.3379pt too wide) in paragraph at lines 13--14 [][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [127 <./PRESENTATION_ExAdv/macc_xilinx_test2c.pdf>] (./presentation.vrb Overfull \hbox (14.22638pt too wide) in paragraph at lines 4--15 [][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [128 <./PRESENTATION_ExAdv/macc_xilinx_test1d.pdf>] (./presentation.vrb Overfull \hbox (14.22638pt too wide) in paragraph at lines 4--15 [][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [129 <./PRESENTATION_ExAdv/macc_xilinx_test2d.pdf>] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [130 <./PRESENTATION_ExAdv/macc_xilinx_test2e.pdf>] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [131] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [132] (./presentation.vrb Overfull \hbox (52.00592pt too wide) in paragraph at lines 24--25 [][][][][][][][][][][][][][][][][] ) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [133] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [134]) (./PRESENTATION_ExOth.tex Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [135] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [136] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [137] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [138] (./presentation.vrb (./PRESENTATION_ExOth/scrambler.v)) Overfull \vbox (12.54794pt too high) detected at line 65 Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [139 <./PRESENTATION_ExOth/scrambler_p01.pdf> <./PRESENTATION_ExOth/scrambler_p 02.pdf pdfTeX warning: pdflatex (file ./PRESENTATION_ExOth/scrambler_p02.pdf): PDF inc lusion: multiple pdfs with page group included in a single page >] (./presentation.vrb) Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [140] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [141] Overfull \hbox (5.77223pt too wide) has occurred while \output is active [][] \T1/lmss/m/n/6 ([]) [142] (./PRESENTATION_ExSyn/techmap_01_map.v) Overfull \vbox (167.4641pt too high) detected at line 131 (./PRESENTATION_ExSyn/techmap_01.v) (./PRESENTATION_ExSyn/techmap_01.ys) Overfull \vbox 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(./PRESENTATION_ExSyn.aux ) (./PRESENTATION_ExAdv.aux) (./PRESENTATION_ExOth.aux) (./PRESENTATION_Prog.aux)) ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathsy.enc}{/usr/sh are/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/usr/share/texli ve/texmf-dist/fonts/enc/dvips/inconsolata/i4-t1-0.enc} Output written on presentation.pdf (169 pages, 892604 bytes). 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Output written on tctt1000.600gf (128 characters, 19540 bytes). Transcript written on tctt1000.log. mktexpk: /build/yosys-cNltON/yosys-0.15/debian/.debhelper/generated/_source/home/.texlive2021/texmf-var/fonts/pk/ljfour/jknappen/ec/tctt1000.600pk: successfully generated. {/usr/share/texlive/texmf-dist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/u sr/share/texmf/fonts/enc/dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/l m/lm-mathit.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texm f/fonts/enc/dvips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/ inconsolata/i4-t1-0.enc}< /usr/share/texlive/texmf-dist/fonts/type1/urw/times/utmr8a.pfb> Output written on manual.pdf (266 pages, 1740343 bytes). Transcript written on manual.log. + false + bibtex manual.aux This is BibTeX, Version 0.99d (TeX Live 2022/dev/Debian) The top-level auxiliary file: manual.aux The style file: alphadin.bst Database file #1: literature.bib Warning--to sort, need author or key in Verilog2005 Warning--to sort, need author or key in VerilogSynth Warning--to sort, need author or key in VHDL Warning--to sort, need author or key in VHDLSynth Warning--to sort, need author or key in IP-XACT Warning--empty pages in Cummings00 Warning--empty pages in intersynthFdlBookChapter Warning--empty author in IP-XACT Warning--empty author in VerilogSynth Warning--empty author in Verilog2005 Warning--empty author in VHDLSynth Warning--empty author in VHDL (There were 12 warnings) + bibtex weblink.aux This is BibTeX, Version 0.99d (TeX Live 2022/dev/Debian) The top-level auxiliary file: weblink.aux The style file: abbrv.bst Database file #1: weblinks.bib Warning--to sort, need author or key in C_to_Verilog Warning--to sort, need author or key in LegUp Warning--to sort, need author or key in flex Warning--to sort, need author or key in bison Warning--to sort, need author or key in LibertyFormat Warning--to sort, need author or key in OR1200 Warning--to sort, need author or key in openMSP430 Warning--to sort, need author or key in i2cmaster Warning--to sort, need author or key in k68 Warning--to sort, need author or key in Formality (There were 10 warnings) + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux CHAPTER_Appnotes.aux CHAPTER_Approach.aux CHAPTER_Auxlibs.aux CHAPTER_Auxprogs.aux CHAPTER_Basics.aux CHAPTER_CellLib.aux CHAPTER_Intro.aux CHAPTER_Optimize.aux CHAPTER_Overview.aux CHAPTER_Prog.aux CHAPTER_Techmap.aux CHAPTER_TextRtlil.aux CHAPTER_Verilog.aux PRESENTATION_ExAdv.aux PRESENTATION_ExOth.aux PRESENTATION_ExSyn.aux PRESENTATION_Intro.aux PRESENTATION_Prog.aux manual.aux presentation.aux weblink.aux manual.bbl weblink.bbl manual.blg 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[261] [262 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [263 <./APPNOTE_010_Verilog_to_ BLIF.pdf>] [264 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [265 <./APPNOTE_011_Design _Investigation.pdf>] [266 <./APPNOTE_011_Design_Investigation.pdf>] [267 <./APP NOTE_011_Design_Investigation.pdf>] [268 <./APPNOTE_011_Design_Investigation.pd f>] [269 <./APPNOTE_011_Design_Investigation.pdf>] [270 <./APPNOTE_011_Design_I nvestigation.pdf>] [271 <./APPNOTE_011_Design_Investigation.pdf>] [272 <./APPNO TE_011_Design_Investigation.pdf>] [273 <./APPNOTE_011_Design_Investigation.pdf> ] [274 <./APPNOTE_012_Verilog_to_BTOR.pdf>] [275 <./APPNOTE_012_Verilog_to_BTOR .pdf>] [276 <./APPNOTE_012_Verilog_to_BTOR.pdf>]) (./manual.bbl [277]) (./weblink.bbl [278]) [279] (./manual.aux (./CHAPTER_Intro.aux) (./CHAPTER_Basics.aux) (./CHAPTER_Approach.aux) (./CHAPTER_Overview.aux) (./CHAPTER_CellLib.aux) (./CHAPTER_Prog.aux) (./CHAPTER_Verilog.aux) (./CHAPTER_Optimize.aux) (./CHAPTER_Techmap.aux) (./CHAPTER_Auxlibs.aux) (./CHAPTER_Auxprogs.aux) (./CHAPTER_TextRtlil.aux) (./CHAPTER_Appnotes.aux)) LaTeX Font Warning: Some font shapes were not available, defaults substituted. LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathsy.enc} {/usr/share/texlive/texmf- dist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/l m/lm-mathit.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texm f/fonts/enc/dvips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/ inconsolata/i4-t1-0.enc}< /usr/share/texmf/fonts/type1/public/lm/lmr5.pfb> Output written on manual.pdf (279 pages, 1842832 bytes). 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[261] [262 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [263 <./APPNOTE_010_Verilog_to_ BLIF.pdf>] [264 <./APPNOTE_010_Verilog_to_BLIF.pdf>] [265 <./APPNOTE_011_Design _Investigation.pdf>] [266 <./APPNOTE_011_Design_Investigation.pdf>] [267 <./APP NOTE_011_Design_Investigation.pdf>] [268 <./APPNOTE_011_Design_Investigation.pd f>] [269 <./APPNOTE_011_Design_Investigation.pdf>] [270 <./APPNOTE_011_Design_I nvestigation.pdf>] [271 <./APPNOTE_011_Design_Investigation.pdf>] [272 <./APPNO TE_011_Design_Investigation.pdf>] [273 <./APPNOTE_011_Design_Investigation.pdf> ] [274 <./APPNOTE_012_Verilog_to_BTOR.pdf>] [275 <./APPNOTE_012_Verilog_to_BTOR .pdf>] [276 <./APPNOTE_012_Verilog_to_BTOR.pdf>]) (./manual.bbl [277]) (./weblink.bbl [278]) [279] (./manual.aux (./CHAPTER_Intro.aux) (./CHAPTER_Basics.aux) (./CHAPTER_Approach.aux) (./CHAPTER_Overview.aux) (./CHAPTER_CellLib.aux) (./CHAPTER_Prog.aux) (./CHAPTER_Verilog.aux) (./CHAPTER_Optimize.aux) (./CHAPTER_Techmap.aux) (./CHAPTER_Auxlibs.aux) (./CHAPTER_Auxprogs.aux) (./CHAPTER_TextRtlil.aux) (./CHAPTER_Appnotes.aux)) LaTeX Font Warning: Some font shapes were not available, defaults substituted. LaTeX Warning: There were undefined references. ) (see the transcript file for additional information){/usr/share/texmf/fonts/enc /dvips/lm/lm-ec.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-mathsy.enc} {/usr/share/texlive/texmf- dist/fonts/enc/dvips/inconsolata/i4-ts1.enc}{/usr/share/texmf/fonts/enc/dvips/l m/lm-mathit.enc}{/usr/share/texmf/fonts/enc/dvips/lm/lm-rm.enc}{/usr/share/texm f/fonts/enc/dvips/lm/lm-ts1.enc}{/usr/share/texlive/texmf-dist/fonts/enc/dvips/ inconsolata/i4-t1-0.enc}< /usr/share/texmf/fonts/type1/public/lm/lmr5.pfb> Output written on manual.pdf (279 pages, 1842832 bytes). Transcript written on manual.log. + md5sum APPNOTE_010_Verilog_to_BLIF.aux APPNOTE_011_Design_Investigation.aux APPNOTE_012_Verilog_to_BTOR.aux CHAPTER_Appnotes.aux CHAPTER_Approach.aux CHAPTER_Auxlibs.aux CHAPTER_Auxprogs.aux CHAPTER_Basics.aux CHAPTER_CellLib.aux CHAPTER_Intro.aux CHAPTER_Optimize.aux CHAPTER_Overview.aux CHAPTER_Prog.aux CHAPTER_Techmap.aux CHAPTER_TextRtlil.aux CHAPTER_Verilog.aux PRESENTATION_ExAdv.aux PRESENTATION_ExOth.aux PRESENTATION_ExSyn.aux PRESENTATION_Intro.aux PRESENTATION_Prog.aux manual.aux presentation.aux weblink.aux manual.bbl weblink.bbl manual.blg weblink.blg + cmp autoloop.old autoloop.new + rm -f autoloop.old + rm -f autoloop.new + grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$' manual.pdf + mv -f manual.pdf.without_pdf_id manual.pdf make[2]: Leaving directory '/build/yosys-cNltON/yosys-0.15' make[1]: Leaving directory '/build/yosys-cNltON/yosys-0.15' dh: command-omitted: The call to "debian/rules override_dh_auto_test" was omitted due to "DEB_BUILD_OPTIONS=nocheck" create-stamp debian/debhelper-build-stamp dh_prep -i debian/rules override_dh_auto_install make[1]: Entering directory '/build/yosys-cNltON/yosys-0.15' dh_auto_install -- GIT_REV=2156e20 ABCEXTERNAL="berkeley-abc" ABCPULL=0 STRIP=: make -j10 install DESTDIR=/build/yosys-cNltON/yosys-0.15/debian/tmp AM_UPDATE_INFO_DIR=no "INSTALL=install --strip-program=true" GIT_REV=2156e20 ABCEXTERNAL=berkeley-abc ABCPULL=0 STRIP=: make[2]: Entering directory '/build/yosys-cNltON/yosys-0.15' [Makefile.conf] CONFIG := gcc mkdir -p /build/yosys-cNltON/yosys-0.15/debian/tmp/usr/bin cp yosys yosys-config yosys-filterlib yosys-smtbmc /build/yosys-cNltON/yosys-0.15/debian/tmp/usr/bin : -S /build/yosys-cNltON/yosys-0.15/debian/tmp/usr/bin/yosys : /build/yosys-cNltON/yosys-0.15/debian/tmp/usr/bin/yosys-filterlib mkdir -p /build/yosys-cNltON/yosys-0.15/debian/tmp/usr/share/yosys cp -r share/. /build/yosys-cNltON/yosys-0.15/debian/tmp/usr/share/yosys/. make[2]: Leaving directory '/build/yosys-cNltON/yosys-0.15' chmod a-x debian/tmp/usr/share/yosys/achronix/speedster22i/cells*.v make[1]: Leaving directory '/build/yosys-cNltON/yosys-0.15' dh_install -i dh_installdocs -i dh_installchangelogs -i debian/rules override_dh_installman make[1]: Entering directory '/build/yosys-cNltON/yosys-0.15' cd debian/man ; CHANGELOG_DATE="26 March 2022" ./genmanpages.sh dh_installman make[1]: Leaving directory '/build/yosys-cNltON/yosys-0.15' dh_python3 -i E: dh_python3 dh_python3:176: no package to act on (python3-foo or one with ${python3:Depends} in Depends) dh_perl -i dh_link -i dh_strip_nondeterminism -i debian/rules override_dh_compress make[1]: Entering directory '/build/yosys-cNltON/yosys-0.15' dh_compress --exclude=.pdf make[1]: Leaving directory '/build/yosys-cNltON/yosys-0.15' dh_fixperms -i dh_missing -i dh_installdeb -i dh_gencontrol -i dh_md5sums -i dh_builddeb -i dpkg-deb: building package 'yosys-doc' in '../yosys-doc_0.15-1_all.deb'. dpkg-genbuildinfo --build=all -O../yosys_0.15-1_all.buildinfo dpkg-genchanges --build=all -O../yosys_0.15-1_all.changes dpkg-genchanges: info: binary-only arch-indep upload (source code and arch-specific packages not included) dpkg-source --after-build . dpkg-buildpackage: info: binary-only upload (no source included) I: running special hook: sync-out /build/yosys-cNltON /tmp/yosys-0.15-1hlyiqglp I: cleaning package lists and apt cache... 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